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publication# ispm4a rev: m amendment/ 0 issue date: september 2006 lead- free package options available! ispmach ? 4a cpld family high performance e 2 cmos ? in-system programmable logic features high-performance, e 2 cmos 3.3-v & 5-v cpld families flexible architecture for rapid logic designs ? excellent first-time-fit tm and re t feature ? speedlocking tm performance for guaranteed xed timing ? central, input and output switch matrices for 100% routability and 100% pin-out retention high speed ? 5.0ns t pd commercial and 7.5ns t pd industrial ? 182mhz f cnt 32 to 512 macrocells; 32 to 768 registers 44 to 388 pins in plcc, pqfp, tqfp, bga, fpbga and cabga packages flexible architecture for a wide range of design styles ? d/t registers and latches ? synchronous or asynchronous mode ? dedicated input registers ? programmable polarity ? reset/ preset swapping advanced capabilities for easy system integration ? 3.3-v & 5-v jedec-compliant operations ? jtag (ieee 1149.1) compliant for boundary scan testing ? 3.3-v & 5-v jtag in-system programming ? pci compliant (-5/-55/-6/-65/-7/-10/-12 speed grades) ? safe for mixed supply voltage system designs ? programmable pull-up or bus-friendly tm inputs and i/os ? hot-socketing ? programmable security bit ? individual output slew rate control advanced e 2 cmos process provides high-performance, cost-effective solutions lead-free package options
2 ispmach 4a family table 1. ispmach 4a device features 3.3 v devices feature m4a3-32 m4a3-64 m4a3-96 m4a3-128 m4a3-192 m4a3-256 m4a3-384 m4a3-512 macrocells 32 64 96 128 192 256 384 512 user i/o options 32 32/64 48 64 96 128/160/192 160/192 160/192/256 t pd (ns) 5.0 5.5 5.5 5.5 6.0 5.5 6.5 7.5 f cnt (mhz) 182 167 167 167 160 167 154 125 t cos (ns) 4.0 4.0 4.0 4.0 4.5 4.0 4.5 5.5 t ss (ns) 3.0 3.5 3.5 3.5 3.5 3.5 3.5 5.0 static power (ma) 20 25/52 40 55 85 110/150 149/155 179 jtag compliant yes yes yes yes yes yes yes yes pci compliant yes yes yes yes yes yes yes yes 5 v devices feature m4a5-32 m4a5-64 m4a5-96 m4a5-128 m4a5-192 m4a5-256 macrocells 32 64 96 128 192 256 user i/o options 32 32 48 64 96 128 t pd (ns) 5.0 5.5 5.5 5.5 6.0 6.5 f cnt (mhz) 182 167 167 167 160 154 t cos (ns) 4.0 4.0 4.0 4.0 4.5 5.0 t ss (ns) 3.0 3.5 3.5 3.5 3.5 3.5 static power (ma) 20 25 40 55 74 110 jtag compliant yes yes yes yes yes yes pci compliant yes yes yes yes yes yes
ispmach 4a family 3 general description the ispmach ? 4a family from lattice offers an exceptionally flexible architecture and delivers a superior complex programmable logic device (cpld) solution of easy-to-use silicon products and software tools. the overall benefits for users are a guaranteed and predictable cpld solution, faster time-to-market, greater flexibility and lower cost. the ispmach 4a devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. the ispmach 4a families offer 5-v (m4a5- xxx) and 3.3-v (m4a3-xxx) operation. ispmach 4a products are 5-v or 3.3-v in-system programmable through the jtag (ieee std. 1149.1) interface. jtag boundary scan testing also allows product testability on automated test equipment for device connectivity. all ispmach 4a family members deliver first-time-fit and easy system integration with pin-out retention after any design change and refit. for both 3.3-v and 5-v operation, ispmach 4a products can deliver guaranteed fixed timing as fast as 5.0 ns t pd and 182 mhz f cnt through the speedlocking feature when using up to 20 product terms per output (table 2). note: 1. c = commercial, i = industrial table 2. ispmach 4a speed grades device speed grade -5 -55 -6 -65 -7 -10 -12 -14 m4a3-32 m4a5-32 c c, i c, i i m4a3-64/32 m4a5-64/32 c c, i c, i i m4a3-64/64 c c, i c, i i m4a3-96 m4a5-96 c c, i c, i i m4a3-128 m4a5-128 c c, i c, i i m4a3-192 m4a5-192 c c, i c, i i m4a3-256/128 c c c, i c, i i m4a5-256/128 c c c, i i m4a3-256/192 m4a3-256/160 c c, i i m4a3-384 c c, i c, i i m4a3-512 c c, i c, i i
4 ispmach 4a family the ispmach 4a family offers 20 density-i/o combinations in thin quad flat pack (tqfp), plastic quad flat pack (pqfp), plastic leaded chip carrier (plcc), ball grid array (bga), fine-pitch bga (fpbga), and chip-array bga (cabga) packages ranging from 44 to 388 pins (table 3). it also offers i/o safety features for mixed-voltage designs so that the 3.3-v devices can accept 5-v inputs, and 5-v devices do not overdrive 3.3-v inputs. additional features include bus-friendly inputs and i/os, a programmable power-down mode for extra power savings and individual output slew rate control for the highest speed transition or for the lowest noise transition. table 3. ispmach 4a package and i/o options (number of i/os and dedicated inputs in table) 3.3 v devices package m4a3-32 m4a3-64 m4a3-96 m4a3-128 m4a3-192 m4a3-256 m4a3-384 m4a3-512 44-pin plcc 32+2 32+2 44-pin tqfp 32+2 32+2 48-pin tqfp 32+2 32+2 100-pin tqfp 64+6 48+8 64+6 100-pin pqfp 64+6 100-ball cabga 64+6 144-pin tqfp 96+16 144-ball fpbga 96+16 208-pin pqfp 128+14, 160 160 160 256-ball fpbga 128+14, 192 192 192 256-ball bga 128+14 192 388-ball fpbga 256 5 v devices package m4a5-32 m4a5-64 m4a5-96 m4a5-128 m4a5-192 m4a5-256 44-pin plcc 32+2 32+2 44-pin tqfp 32+2 32+2 48-pin tqfp 32+2 32+2 100-pin tqfp 48+8 64+6 100-pin pqfp 64+6 144-pin tqfp 96+16 208-pin pqfp 128+14
ispmach 4a family 5 functional description the fundamental architecture of ispmach 4a devices (figure 1) consists of multiple, optimized pal ? blocks interconnected by a central switch matrix. the central switch matrix allows communication between pal blocks and routes inputs to the pal blocks. together, the pal blocks and central switch matrix allow the logic designer to create large designs in a single device instead of having to use multiple devices. the key to being able to make effective use of these devices lies in the interconnect schemes. in the ispmach 4a architecture, the macrocells are flexibly coupled to the product terms through the logic allocator, and the i/o pins are flexibly coupled to the macrocells due to the output switch matrix. in addition, more input routing options are provided by the input switch matrix. these resources provide the flexibility needed to fit designs efficiently. notes: 1. 16 for ispmach 4a devices with 1:1 macrocell-i/o cell ratio (see next page). 2. block clocks do not go to i/o cells in m4a(3,5)-32/32. 3. m4a(3,5)-192, m4a(3,5)-256, m4a3-384, and m4a3-512 have dedicated clock pins which cannot be used as inputs and do not connec t to the central switch matrix. i/o pins clock/input pins central switch matrix i/o pins i/o pins dedicated input pins pal block pal block logic allocator with xor output/ buried macrocells 33/ 34/ 36 16 16 clock generator logic array output switch matrix input switch matrix i/o cells 16 16 8 note 1 note 2 note 3 4 pal block 17466g-001 figure 1. ispmach 4a block diagram and pal block structure
6 ispmach 4a family table 4. architectural summary of ispmach 4a devices the macrocell-i/o cell ratio is defined as the number of macrocells versus the number of i/o cells internally in a pal block (table 4). the central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the pal blocks. feedback signals that return to the same pal block still must go through the central switch matrix. this mechanism ensures that pal blocks in ispmach 4a devices communicate with each other with consistent, predictable delays. the central switch matrix makes a ispmach 4a device more advanced than simply several pal devices on a single chip. it allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into pal blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device. each pal block consists of: product-term array logic allocator macrocells output switch matrix i/o cells input switch matrix clock generator notes: 1. m4a3-64/64 internal switch matrix functionality embedded in central switch matrix. ispmach 4a devices m4a3-64/32, m4a5-64/32 m4a3-96/48, m4a5-96/48 m4a3-128/64, m4a5-128/64 m4a3-192/96, m4a5-192/96 m4a3-256/128, m4a5-256/128 m4a3-384 m4a3-512 m4a3-32/32 m4a5-32/32 m4a3-64/64 m4a3-256/160 m4a3-256/192 macrocell-i/o cell ratio 2:1 1:1 input switch matrix yes yes 1 input registers yes no central switch matrix yes yes output switch matrix yes yes
ispmach 4a family 7 product-term array the product-term array consists of a number of product terms that form the basis of the logic being implemented. the inputs to the and gates come from the central switch matrix (table 5), and are provided in both true and complement forms for efficient logic implementation. logic allocator within the logic allocator, product terms are allocated to macrocells in ?product term clusters.? the availability and distribution of product term clusters are automatically considered by the software as it fits functions within a pal block. the size of a product term cluster has been optimized to provide high utilization of product terms, making complex functions using many product terms possible. yet when few product terms are used, there will be a minimal number of unused?or wasted?product terms left over. the product term clusters available to each macrocell within a pal block are shown in tables 6 and 7. each product term cluster is associated with a macrocell. the size of a cluster depends on the configuration of the associated macrocell. when the macrocell is used in synchronous mode (figure 2a), the basic cluster has 4 product terms. when the associated macrocell is used in asynchronous mode (figure 2b), the cluster has 2 product terms. note that if the product term cluster is routed to a different macrocell, the allocator configuration is not determined by the mode of the macrocell actually being driven. the configuration is always set by the mode of the macrocell that the cluster will drive if not routed away, reg ardless of the actual routing. in addition, there is an extra product term that can either join the basic cluster to give an extended cluster, or drive the second input of an exclusive-or gate in the signal path. if included with the basic cluster, this provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term clusters. a similar asynchronous function can have up to 18 product terms. when the extra product term is used to extend the cluster, the value of the second xor input can be programmed as a 0 or a 1, giving polarity control. the possible configurations of the logic allocator are shown in figures 3 and 4. table 5. pal block inputs device number of inputs to pal block m4a3-32/32 and m4a5-32/32 m4a3-64/32 and m4a5-64/32 m4a3-64/64 m4a3-96/48 and m4a5-96/48 m4a3-128/64 and m4a5-128/64 33 33 33 33 33 m4a3-192/96 and m4a5-192/96 m4a3-256/128 and m4a5-256/128 34 34 m4a3-256/160 and m4a3-256/192 m4a3-384 m4a3-512 36 36 36
8 ispmach 4a family table 6. logic allocator for all ispmach 4a devices (except m4a(3,5)-32/32) output macrocell available clusters output macrocell available clusters m 0 c 0 , c 1 , c 2 m 8 c 7 , c 8 , c 9 , c 10 m 1 c 0 , c 1 , c 2 , c 3 m 9 c 8 , c 9 , c 10 , c 11 m 2 c 1 , c 2 , c 3 , c 4 m 10 c 9 , c 10 , c 11 , c 12 m 3 c 2 , c 3 , c 4 , c 5 m 11 c 10 , c 11 , c 12 , c 13 m 4 c 3 , c 4 , c 5 , c 6 m 12 c 11 , c 12 , c 13 , c 14 m 5 c 4 , c 5 , c 6 , c 7 m 13 c 12 , c 13 , c 14 , c 15 m 6 c 5 , c 6 , c 7 , c 8 m 14 c 13 , c 14 , c 15 m 7 c 6 , c 7 , c 8 , c 9 m 15 c 14 , c 15 table 7. logic allocator for m4a(3,5)-32/32 output macrocell available clusters output macrocell available clusters m 0 c 0 , c 1 , c 2 m 8 c 8 , c 9 , c 10 m 1 c 0 , c 1 , c 2 , c 3 m 9 c 8 , c 9 , c 10 , c 11 m 2 c 1 , c 2 , c 3 , c 4 m 10 c 9 , c 10 , c 11 , c 12 m 3 c 2 , c 3 , c 4 , c 5 m 11 c 10 , c 11 , c 12 , c 13 m 4 c 3 , c 4 , c 5 , c 6 m 12 c 11 , c 12 , c 13 , c 14 m 5 c 4 , c 5 , c 6 , c 7 m 13 c 12 , c 13 , c 14 , c 15 m 6 c 5 , c 6 , c 7 m 14 c 13 , c 14 , c 15 m 7 c 6 , c 7 m 15 c 14 , c 15 0 default 0 default prog. polarity to n-1 to n-2 from n-1 to n+1 from n+1 from n+2 basic product term cluster extra product term logic allocator n n to macrocell n 0 default 0 default prog. polarity to n-1 to n-2 from n-1 to n+1 from n+1 from n+2 basic product term cluster extra product term logic allocator nn to macrocell n 17466g-006 figure 2. logic allocator: con guration of cluster ?n? set by mode of macrocell ?n? 17466g-005 a. synchronous mode b. asynchronous mode
ispmach 4a family 9 note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. all configurations have the same delay. this means that designers do not have to decide between optimizing resources or speed; both can be optimized. if not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide xor logic for such functions as data comparison, or it can work with the d-,t-type flip-flop to provide for j-k, and s-r register operation. in addition, if the basic cluster is routed to another macrocell, the extra product term is still available for logic. in this case, the first xor input will be a logic 0. this circuit has the flexibility to route product terms elsewhere without giving up the use of the macrocell. product term clusters do not ?wrap? around a pal block. this means that the macrocells at the ends of the block have fewer product terms available. 0 17466g-007 figure 3. logic allocator con gurations: synchronous mode a. basic cluster with xor b. extended cluster, active high c. extended cluster, active low d. basic cluster routed away; single-product-term, active high e. extended cluster routed away 0 17466g-008 figure 4. logic allocator con gurations: asynchronous mode b. extended cluster, active high c. extended cluster, active low e. extended cluster routed away d. basic cluster routed away; single-product-term, active high a. basic cluster with xor
10 ispmach 4a family macrocell the macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. the macrocell has two fundamental modes: synchronous and asynchronous (figure 5). the mode chosen only affects clocking and initialization in the macrocell. in either mode, a combinatorial path can be used. for combinatorial logic, the synchronous mode will generally be used, since it provides more product terms in the allocator. swap d/t/l q ap ar power-up reset pal-block initialization product terms from logic allocator block clk0 block clk1 block clk2 block clk3 to output and input switch matrices common pal-block resource individual macrocell resources from pal-clock generator d/t/l q ap ar power-up reset individual initialization product term from logic allocator block clk0 block clk1 to output and input switch matrices individual clock product term from pal-block clock generator swap 17466g-010 figure 5. macrocell 17466g-009 a. synchronous mode b. asynchronous mode
ispmach 4a family 11 the flip-flop can be configured as a d-type or t-type latch. j-k or s-r registers can be synthesized. the primary flip-flop configurations are shown in figure 6, although others are possible. flip-flop functionality is defined in table 8. note that a j-k latch is inadvisable as it will cause oscillation if both j and k inputs are high. dq ap ar dq ap ar lq ap ar lq ap ar g g tq ap ar 17466g-011 figure 6. primary macrocell con gurations g. combinatorial with programmable polarity a. d-type with xor b. d-type with programmable d polarity c. latch with xor d. latch with programmable d polarity e. t-type with programmable t polarity f. combinatorial with xor
12 ispmach 4a family note: 1. polarity of clk/le can be programmed although the macrocell shows only one input to the register, the xor gate in the logic allocator allows the d-, t-type register to emulate j-k, and s-r behavior. in this case, the available product terms are divided between j and k (or s and r). when configured as j-k, s-r, or t-type, the extra product term must be used on the xor gate input for flip-flop emulation. in any register type, the polarity of the inputs can be programmed. the clock input to the flip-flop can select any of the four pal block clocks in synchronous mode, with the additional choice of either polarity of an individual product term clock in the asynchronous mode. the initialization circuit depends on the mode. in synchronous mode (figure 7), asynchronous reset and preset are provided, each driven by a product term common to the entire pal block. table 8. register/latch operation con?uration input(s) clk/le 1 q+ d-type register d=x d=0 d=1 0,1, ( ) ( ) ( ) q 0 1 t-type register t=x t=0 t=1 0, 1, ( ) ( ) ( ) q q q d-type latch d=x d=0 d=1 1(0) 0(1) 0(1) q 0 1 power-up reset ap d/t/l ar q pal-block initialization product terms a. power-up reset power-up preset ap d/l pal-block initialization product terms ar q 17466g-012 17466g-013 figure 7. synchronous mode initialization con gurations b. power-up preset
ispmach 4a family 13 a reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. in asynchronous mode (figure 8), a single individual product term is provided for initialization. it can be selected to control reset or preset. note that the reset/preset swapping selection feature effects power-up reset as well. the initialization functionality of the flip-flops is illustrated in table 9. the macrocell sends its data to the output switch matrix and the input switch matrix. the output switch matrix can route this data to an output if so desired. the input switch matrix can send the signal back to the central switch matrix as feedback. note: 1. transparent latch is unaffected by ar, ap table 9. asynchronous reset/preset operation ar ap clk/le 1 q+ 0 0 x see table 8 01x1 10x0 11x0 power-up reset ap d/l/t ar q individual reset product term a. reset power-up preset ap d/l/t ar q individual preset product term b. preset 17466g-014 17466g-015 figure 8. asynchronous mode initialization con gurations
14 ispmach 4a family output switch matrix the output switch matrix allows macrocells to be connected to any of several i/o cells within a pal block. this provides high flexibility in determining pinout and allows design changes to occur without effecting pinout. in ispmach 4a devices with 2:1 macrocell-i/o cell ratio, each pal block has twice as many macrocells as i/o cells. the ispmach 4a output switch matrix allows for half of the macrocells to drive i/o cells within a pal block, in combinations according to figure 9. each i/o cell can choose from eight macrocells; each macrocell has a choice of four i/o cells. the ispmach 4a devices with 1:1 macrocell-i/o cell ratio allow each macrocell to drive one of eight i/o cells (figure 9). table 10. output switch matrix combinations for ispmach 4a devices with 2:1 macrocell-i/o cell ratio macrocell routable to i/o cells m0, m1 i/o0, i/o5, i/o6, i/o7 m2, m3 i/o0, i/o1, i/o6, i/o7 m4, m5 i/o0, i/o1, i/o2, i/o7 m6, m7 i/o0, i/o1, i/o2, i/o3 m8, m9 i/o1, i/o2, i/o3, i/o4 m10, m11 i/o2, i/o3, i/o4, i/o5 m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 each macrocell can drive one of 4 i/o cells in ispmach 4a devices with 2:1 macrocell-i/o cell ratio. each i/o cell can choose one of 8 macrocells in all ispmach 4a devices. macrocells mux i/o cell m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 each macrocell can drive one of 8 i/o cells in ispmach 4a devices with 1:1 macrocell-i/o cell ratio except m4a(3, 5)-32/32 devices. m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 each macrocell can drive one of 8 i/o cells in m4a(3, 5)-32/32 devices. figure 9. ispmach 4a output switch matrix
ispmach 4a family 15 m12, m13 i/o3, i/o4, i/o5, i/o6 m14, m15 i/o4, i/o5, i/o6, i/o7 i/o cell available macrocells i/o0 m0, m1, m2, m3, m4, m5, m6, m7 i/o1 m2, m3, m4, m5, m6, m7, m8, m9 i/o2 m4, m5, m6, m7, m8, m9, m10, m11 i/o3 m6, m7, m8, m9, m10, m11, m12, m13 i/o4 m8, m9, m10, m11, m12, m13, m14, m15 i/o5 m0, m1, m10, m11, m12, m13, m14, m15 i/o6 m0, m1, m2, m3, m12, m13, m14, m15 i/o7 m0, m1, m2, m3, m4, m5, m14, m15 table 11. output switch matrix combinations for m4a3-256/160 and m4a3-256/192 macrocell routable to i/o cells m0 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 m1 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 m2 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 m3 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 m4 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 m5 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 m6 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 m7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 m8 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 m9 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 m10 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 m11 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 m12 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 m13 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 m14 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 m15 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o cell available macrocells i/o0 m0 m1 m2 m3 m4 m5 m6 m7 i/o1 m0 m1 m2 m3 m4 m5 m6 m7 i/o2 m0 m1 m2 m3 m4 m5 m6 m7 i/o3 m0 m1 m2 m3 m4 m5 m6 m7 i/o4 m0 m1 m2 m3 m4 m5 m6 m7 i/o5 m0 m1 m2 m3 m4 m5 m6 m7 i/o6 m0 m1 m2 m3 m4 m5 m6 m7 i/o7 m0 m1 m2 m3 m4 m5 m6 m7 table 10. output switch matrix combinations for ispmach 4a devices with 2:1 macrocell-i/o cell ratio macrocell routable to i/o cells
16 ispmach 4a family table 13. output switch matrix combinations for m4a3-64/64 i/o8 m8 m9 m10 m11 m12 m13 m14 m15 i/o9 m8 m9 m10 m11 m12 m13 m14 m15 i/o10 m8 m9 m10 m11 m12 m13 m14 m15 i/o11 m8 m9 m10 m11 m12 m13 m14 m15 i/o12 m8 m9 m10 m11 m12 m13 m14 m15 i/o13 m8 m9 m10 m11 m12 m13 m14 m15 i/o14 m8 m9 m10 m11 m12 m13 m14 m15 i/o15 m8 m9 m10 m11 m12 m13 m14 m15 table 12. output switch matrix combinations for m4a(3,5)-32/32 macrocell routable to i/o cells m0, m1, m2, m3, m4, m5, m6, m7 i/o0, i/o1, i/o2, i/o3, i/o4, i/o5, i/o6, i/o7 m8, m9, m10, m11, m12, m13, m14, m15 i/o8, i/o9, i/o10, i/o11, i/o12, i/o13, i/o14, i/o15 i/o cell available macrocells i/o0, i/o1, i/o2, i/o3, i/o4, i/o5, i/o6, i/o7 m0, m1, m2, m3, m4, m5, m6, m7 i/o8, i/o9, i/o10, i/o11, i/o12, i/o13, i/o14, i/o15 m8, m9, m10, m11, m12, m13, m14, m15 macrocell routable to i/o cells mo, m1 i/o0, i/o1, i/o10, i/o11, i/o12, i/o13, i/o14, i/o15 m2, m3 i/o0, i/o1, i/o2, i/o3, i/o12, i/o13, i/o14, i/o15 m4, m5 i/o0, i/o1, i/o2,i/o3, i/o4,i/o5, i/o14, i/o15 m6, m7 i/o0, i/o1, i/o2, i/o3, i/o4, i/o5, i/o6, i/o7 m8, m9 i/o2, i/o3, i/o4, i/o5, i/o6, i/o7, i/o8, i/o9 m10, m11 i/o4, i/o5, i/o6, i/o7, i/o8, i/o9, i/o10, i/o11 m12, m13 i/o6, i/o7, i/o8, i/o9, i/o10, i/o11, i/o12, i/o13 m14, m15 i/o8, i/o9, i/o10, i/o11, i/o12, i/o13, i/o14, i/o15 i/o cell available macrocells i/o0, i/o1 m0, m1, m2, m3, m4, m5, m6, m7 i/o2, i/o3 m2, m3, m4, m5, m6, m7, m8, m9 i/o4, i/o5 m4, m5, m6, m7, m8, m9, m10, m11 i/o6, i/o7 m6, m7, m8, m9, m10, m11, m12, m13 i/o8, i/o9 m8, m9, m10, m11, m12, m13, m14, m15 i/o10, i/o11 m0, m1, m10, m11, m12, m13, m14, m15 i/o12, i/o13 m0, m1, m2, m3, m12, m13, m14, m15 i/o14, i/o15 m0, m1, m2, m3, m4, m5, m14, m15 table 11. output switch matrix combinations for m4a3-256/160 and m4a3-256/192 macrocell routable to i/o cells
ispmach 4a family 17 i/o cell the i/o cell (figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except ispmach 4a devices with 1:1 macrocell-i/o cell ratio). an individual output enable product term is provided for each i/o cell. the feedback signal drives the input switch matrix. the i/o cell (figure 10) contains a flip-flop, which provides the capability for storing the input in a d-type register or latch. the clock can be any of the pal block clocks. both the direct and registered versions of the input are sent to the input switch matrix. this allows for such functions as ?time-domain-multiplexed? data comparison, where the first data value is stored, and then the second data value is put on the i/o pin and compared with the previous stored value. note that the flip-flop used in the ispmach 4a i/o cell is independent of the flip-flops in the macrocells. it powers up to a logic low. zero-hold-time input register the ispmach 4a devices have a zero-hold-time (zht) fuse which controls the time delay associated with loading data into all i/o cell registers and latches. when programmed, the zht fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. when the fuse is erased, the setup time to the input storage element is minimized. this feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges. d/l q block clk3 block clk2 block clk1 block clk0 to input switch matrix individual output enable product term from output switch matrix 17466g-017 17466g-018 figure 10. i/o cell for ispmach 4a devices with 2:1 macrocell-i/o cell ratio figure 11. i/o cell for ispmach 4a devices with 1:1 macrocell-i/o cell ratio to input switch matrix individual output enable product term from output switch matrix power-up reset
18 ispmach 4a family input switch matrix the input switch matrix (figures 12 and 13) optimizes routing of inputs to the central switch matrix. without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. the input switch matrix provides additional ways for these signals to enter the central switch matrix. to central switch matrix from macrocell 2 from input cell direct from macrocell 1 registered/latched 17466g-002 17466g-003 figure 12. ispmach 4a with 2:1 macrocell-i/o cell ratio - input switch matrix figure 13. ispmach 4a with 1:1 macrocell-i/o cell ratio - input switch matrix to central switch matrix from macrocell from i/o pin
ispmach 4a family 19 pal block clock generation each ispmach 4a device has four clock pins that can also be used as inputs. these pins drive a clock generator in each pal block (figure 14). the clock generator provides four clock signals that can be used anywhere in the pal block. these four pal block clock signals can consist of a large number of combinations of the true and complement edges of the global clock signals. table 14 lists the possible combinations. 1. m4a(3,5)-32/32 and m4a(3,5)-64/32 have only two clock pins, gclk0 and gclk1. gclk2 is tied to gclk0, and gclk3 is tied to gcl k1. note: 1. values in parentheses are for the m4a(3,5)-32/32 and m4a(3,5)-64/32. this feature provides high flexibility for partitioning state machines and dual-phase clocks. it also allows latches to be driven with either polarity of latch enable, and in a master-slave configuration. table 14. pal block clock combinations 1 block clk0 block clk1 block clk2 block clk3 gclk0 gclk1 gclk0 gclk1 x x x x gclk1 gclk1 gclk0 gclk0 x x x x x x x x gclk2 (gclk0) gclk3 (gclk1 ) gclk2 (gclk0) gclk3 (gclk1 ) x x x x gclk3 (gclk1) gclk3 (gclk1) gclk2 (gclk0 ) gclk2 (gclk0 ) gclk0 gclk1 gclk2 gclk3 block clk0 (gclk0 or gclk1) block clk1 (gclk1 or gclk0) block clk2 (gclk2 or gclk3) block clk3 (gclk3 or gclk2) 17466g-004 figure 14. pal block clock generator 1
20 ispmach 4a family ispmach 4a timing model the primary focus of the ispmach 4a timing model is to accurately represent the timing in a ispmach 4a device, and at the same time, be easy to understand. this model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. a signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. the input register specifications are also reported as internal feedback. when a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. the parameter, t buf , is defined as the time it takes to go from feedback through the output buffer to the i/o pad. if a signal goes to the internal feedback rather than to the i/o pad, the parameter designator is followed by an ?i?. by adding t buf to this internal parameter, the external parameter is derived. for example, t pd = t pdi + t buf . a diagram representing the modularized ispmach 4a timing model is shown in figure 15. refer to the application note entitled mach 4 timing and high speed design for a more detailed discussion about the timing parameters. speedlocking for guaranteed fixed timing the ispmach 4a architecture allows allocation of up to 20 product terms to an individual macrocell with the assistance of an xor gate without incurring additional timing delays. the design of the switch matrix and pal blocks guarantee a fixed pin-to-pin delay that is independent of the logic required by the design. other competitive cplds incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. speed and speedlocking combine to give designs easy access to the performance required in today?s designs. (external feedback) (internal feedback) input reg/ input latch t sirs t hirs t sil t hil t sirz t hirz t silz t hilz t pdili t icosi t igosi t pdilzi q t ss(t) t sa(t) t h(s/a) t s(s/a)l t h(s/a)l t srr t pdi t pdli t co(s/a)i t go(s/a)i t sri comb/dff/tff/ latch/sr*/jk* s/r in blk clk out t pl t buf t ea t er t slw q central switch matrix *emulated 17466g-025 figure 15. ispmach 4a timing model
ispmach 4a family 21 ieee 1149.1-compliant boundary scan testability all ispmach 4a devices have boundary scan cells and are compliant to the ieee 1149.1 standard. this allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. in addition, these devices can be linked into a board-level serial scan path for more complete board-level testing. ieee 1149.1-compliant in-system programming programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. all ispmach 4a devices provide in-system programming (isp) capability through their boundary scantest access ports. this capability has been implemented in a manner that ensures that the port remains compliant to the ieee 1149.1 standard. by using ieee 1149.1 as the communication interface through which isp is achieved, customers get the benefit of a standard, well-defined interface. ispmach 4a devices can be programmed across the commercial temperature and voltage range. the pc- based ispvm? software facilitates in-system programming of ispmach 4a devices. ispvm takes the jedec file output produced by the design implementation software, along with information about the jtag chain, and creates a set of vectors that are used to drive the jtag chain. ispvm software can use these vectors to drive a jtag chain via the parallel port of a pc. alternatively, ispvm software can output files in formats understood by common automated test equipment. this equpment can then be used to program ispmach 4a devices during the testing of a circuit board. pci compliant ispmach 4a devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the pci local bus specification version 2.1, published by the pci special interest group (sig). the 5-v devices are fully pci- compliant. the 3.3-v devices are mostly compliant but do not meet the pci condition to clamp the inputs as they rise above v cc because of their 5-v input tolerant feature. safe for mixed supply voltage system designs both the 3.3-v and 5-v v cc ispmach 4a devices are safe for mixed supply voltage system designs. the 5-v devices will not overdrive 3.3-v devices above the output voltage of 3.3 v, while they accept inputs from other 3.3-v devices. the 3.3-v device will accept inputs up to 5.5 v. both the 5-v and 3.3-v versions have the same high-speed performance and provide easy-to-use mixed-voltage design capability. pull up or bus-friendly inputs and i/os all ispmach 4a devices have inputs and i/os which feature the bus-friendly circuitry incorporating two inverters in series which loop back to the input. this double inversion weakly holds the input at its last driven logic state. while it is good design practice to tie unused pins to a known state, the bus-friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. at power-up, the bus-friendly latches are reset to a logic level ?1.? for the circuit diagram, please refer to the document entitled mach endurance characteristics on the lattice data book cd-rom or lattice web site. all ispmach 4a devices have a programmable bit that configures all inputs and i/os with either pull-up or bus-friendly characteristics. if the device is configured in pull-up mode, all inputs and i/o pins are
22 ispmach 4a family weakly pulled up. for the circuit diagram, please refer to the document entitled mach endurance characteristics on the lattice data book cd-rom or lattice web site. power management each individual pal block in ispmach 4a devices features a programmable low-power mode, which results in power savings of up to 50%. the signal speed paths in the low-power pal block will be slower than those in the non-low-power pal block. this feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode. programmable slew rate each ispmach 4a device i/o has an individually programmable output slew rate control bit. each output can be individually configured for the higher speed transition (3 v/ns) or for the lower noise transition (1 v/ns). for high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. for designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. the slew rate is adjusted independent of power. power-up reset/set all flip-flops power up to a known state for predictable system initialization. if a macrocell is configured to set on a signal from the control generator, then that macrocell will be set during device power-up. if a macrocell is configured to reset on a signal from the control generator or is not configured for set/reset, then that macrocell will reset on power-up. to guarantee initialization values, the v cc rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. security bit a programmable security bit is provided on the ispmach 4a devices as a deterrent to unauthorized copying of the array configuration patterns. once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. programming and verification are also defeated by the security bit. the bit can only be reset by erasing the entire device. hot socketing ispmach 4a devices are well-suited for those applications that require hot socketing capability. hot socketing a device requires that the device, when powered down, can tolerate active signals on the i/os and inputs without being damaged. additionally, it requires that the effects of the powered-down mach devices be minimal on active signals.
ispmach 4a family 23 macrocell m0 c0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 b 89 m0 m4a(3, 5)-64/32 m4a3-64/64 m4a(3, 5)-96/48 m4a(3, 5)-128/64 a b 16 17 17 17 m4(3, 5)-192/96 m4(3, 5)-256/128 m4a3-384 m4a3-512 18 18 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 o0 o1 o2 o3 o4 o5 o6 o7 m15 clk0 clk1 clk2 clk3 i/o cell i/o0 clock generator macrocell macrocell macrocell macrocell macrocell macrocell central switch matrix macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell 24 a 0 4 16 16 c1 c2 i/o cell i/o1 c3 c4 i/o cell i/o2 c5 c6 i/o cell i/o3 c7 c8 i/o cell i/o4 c9 c10 i/o cell i/o5 c11 c12 i/o cell i/o6 c13 c14 i/o cell input switch matrix i/o7 c15 logic allocator output switch matrix figure 16. pal block for ispmach 4a with 2:1 macrocell - i/o cell ratio
24 ispmach 4a family figure 17. pal block for ispmach 4a devices with 1:1 macrocell-i/o cell ratio (except m4a (3,5)-32/32) macrocell m0 c0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 b 97 m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 o0 o2 o4 o6 o8 o10 o12 o14 m15 i/o cell i/o0 clock generator macrocell macrocell macrocell macrocell macrocell macrocell central switch matrix macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell o1 i/o cell i/o1 32 a 0 4 16 16 c1 c2 i/o cell i/o2 o3 i/o cell i/o3 o5 i/o cell i/o5 o7 i/o cell i/o7 c3 c4 i/o cell i/o4 c5 c6 i/o cell i/o6 c7 c8 i/o cell i/o8 o9 i/o cell i/o9 o11 i/o cell i/o11 c9 c10 i/o cell i/o10 c11 c12 i/o cell i/o12 o13 i/o cell i/o13 o15 i/o cell i/o15 c13 c14 i/o cell input switch matrix i/o14 c15 logic allocator output switch matrix clk0 clk1 clk2 clk3 m4a3-64/64 a b 16 17 18 18 m4a3-256/160 m4a3-256/192 17466h-41
ispmach 4a family 25 17466h-042 macrocell m0 c0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 17 97 m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 o0 o2 o4 o6 o8 o10 o12 o14 m15 i/o cell i/o0 clock generator macrocell macrocell macrocell macrocell macrocell macrocell central switch matrix macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell o1 i/o cell i/o1 32 16 0 2 16 16 c1 c2 i/o cell i/o2 o3 i/o cell i/o3 o5 i/o cell i/o5 o7 i/o cell i/o7 c3 c4 i/o cell i/o4 c5 c6 i/o cell i/o6 c7 c8 i/o cell i/o8 o9 i/o cell i/o9 o11 i/o cell i/o11 c9 c10 i/o cell i/o10 c11 c12 i/o cell i/o12 o13 i/o cell i/o13 o15 i/o cell i/o15 c13 c14 i/o cell input switch matrix i/o14 c15 logic allocator output switch matrix output switch matrix clk0/i0 clk0/i1 figure 18. pal block for m4a (3,5)-32/32
26 ispmach 4a family block diagram ? m4a(3,5)-32/32 17466h-019 central switch matrix 2 2 clk0/i0, clk1/i1 i/o8?/o15 i/o0?/o7 i/o16?/o23 i/o24?/o31 i/o cells output switch matrix macrocells 8 8 16 8 8 8 33 4 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 98 and logic array and logic allocator clock generator input switch matrix 8 8 16 8 8 8 2 8 8 i/o cells output switch matrix macrocells 8 8 16 8 8 8 8 8 i/o cells output switch matrix macrocells 66 x 98 and logic array and logic allocator 8 8 16 8 8 8 2 8 8 input switch matrix input switch matrix input switch matrix clock generator oe oe oe oe block a block b 33
ispmach 4a family 27 block diagram ? m4a(3,5)-64/32 17466h-020 central switch matrix 2 2 clk0/i0, clk1/i1 i/o0?/o7 i/o24?/o31 i/o16?/o23 i/o8?/o15 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator 16 16 24 16 16 8 33 4 4 2 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 2 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 2 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 2 8 8 input switch matrix input switch matrix input switch matrix clock generator clock generator oe oe oe oe block a block b block d block c
28 ispmach 4a family block diagram ? m4a3-64/64 central switch matrix 4 4 clk0/i0, clk1/i1 clk2/i3, clk3/i4 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator 16 16 16 16 16 33 4 4 16 16 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator 16 16 16 16 16 33 4 4 16 16 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 16 16 16 33 4 4 16 16 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 16 16 16 33 4 4 16 16 clock generator clock generator oe oe oe oe block a block b block d block c 2 17466h-020a
ispmach 4a family 29 block diagram ? m4a(3,5)-96/48 4 4 4 clk0/i0, clk1/i1, clk2/i4, clk3/i5 i2, i3, i6, i7 i/o16?/o23 i/o8?/o15 i/o0?/o7 i/o40?/o47 i/o32?/o39 i/o24?/o31 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 oe input switch matrix input switch matrix input switch matrix clock generator clock generator clock generator input switch matrix oe oe oe oe oe block c block b block a block d block e block f central switch matrix 17466g-021
ispmach 4a family 30 block diagram ? m4a(3,5)-128/64 central switch matrix 4 4 2 clk0/i0, clk1/i1, clk2/i3, clk3/i4 i2, i5 i/o0?/o7 i/o8?/o15 i/o16?/o23 i/o24?/031 i/o32?/o39 i/o40?/o47 i/o48?/o55 i/o56?/o63 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator oe 16 16 24 16 16 8 33 4 4 4 8 8 input switch matrix input switch matrix input switch matrix clock generator clock generator clock generator input switch matrix input switch matrix clock generator oe oe oe oe oe oe oe block a block b block c block d block h block g block f block e 17466h-022
ispmach 4a family 31 block diagram ? m4a(3,5)-192/96 central switch matrix block b i/o88?/o95 clk0?lk3 i/o16?/o23 block e i/o40?/o47 block h i/o32?/o39 block g i0?15 i/o24?/o31 block f block a i/o80?/o87 block k i/o64?/o71 block l i/o72?/o79 block c i/o8?/o15 block d i/o0?/o7 i/o56?/o63 block j i/o48?/o55 block i i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix 16 4 4 oe 8 16 8 4 16 24 8 16 16 34 4 4 8 24 34 4 8 8 16 16 4 4 16 16 oe 8 24 34 4 8 8 16 16 4 4 16 16 oe 8 16 8 4 16 24 8 16 16 34 34 34 34 34 34 34 34 34 4 4 oe oe 8 16 8 4 16 24 8 16 16 4 4 8 24 4 8 8 16 16 4 4 16 16 oe 8 24 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 24 16 16 8 16 8 4 16 oe 4 4 24 16 16 8 16 16 4 8 8 oe 4 4 24 16 16 8 16 16 4 8 8 4 4 8 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 4 4 oe 17466g-067
32 ispmach 4a family block diagram ? m4a(3,5)-256/128 central switch matrix block b i/o8?/o15 clk0?lk3 i/o48?/o55 block g i/o72?/o79 block j i/o64?/o71 block i i0?13 i/o56?/o63 block h block a i/o0?/o7 block o i/o112?/o119 block p i/o120?/o127 block c i/o16?/o23 block d i/o24?/o31 block e i/o32?/o39 block f i/o40?/o47 i/o104?/o111 block n i/o96?/o103 block m i/o88?/o95 block l i/o80?/o87 block k i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix 14 4 4 oe 8 16 8 4 16 24 8 16 16 34 4 4 8 24 34 4 8 8 16 16 4 4 16 16 oe 8 24 34 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 34 24 16 16 8 16 8 4 16 oe 4 4 34 24 16 16 8 16 16 4 8 8 oe 4 4 34 24 16 16 8 16 16 4 8 8 4 4 8 34 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 34 4 4 oe oe 8 16 8 4 16 24 8 16 16 34 4 4 8 24 34 4 8 8 16 16 4 4 16 16 oe 8 24 34 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 34 24 16 16 8 16 8 4 16 oe 4 4 34 24 16 16 8 16 16 4 8 8 oe 4 4 34 24 16 16 8 16 16 4 8 8 4 4 8 34 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 34 4 4 oe 17466g-024
ispmach 4a family 33 block diagram ? m4a3-256/160, m4a3-256/192 central switch matrix block b clk0?lk3 block g block j block i block h block a block o block p block c block d block e block f block n block m block l block k i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 98 and logic array and logic allocator clock generator input switch matrix output switch matrix 4 4 oe 16 16 16 4 16 32 16 16 16 36 4 4 16 32 36 4 16 16 16 16 4 4 16 16 oe 16 32 36 4 16 16 16 16 4 4 16 16 oe oe 4 4 16 36 32 16 16 16 16 16 4 16 oe 4 4 36 32 16 16 16 16 16 4 16 16 oe 4 4 36 32 16 16 16 16 16 4 16 16 4 4 16 36 32 16 16 16 16 16 4 16 oe 16 16 16 4 16 32 16 16 16 36 4 4 oe oe 16 16 16 4 16 32 16 16 16 36 4 4 16 32 36 4 16 16 16 16 4 4 16 16 oe 16 32 36 4 16 16 16 16 4 4 16 16 oe oe 4 4 16 36 32 16 16 16 16 16 4 16 oe 4 4 36 32 16 16 16 16 16 4 16 16 oe 4 4 36 32 16 16 16 16 16 4 16 16 4 4 16 36 32 16 16 16 16 16 4 16 oe 16 16 16 4 16 32 16 16 16 36 4 4 oe 17466g-050
34 ispmach 4a family block diagram ? m4a3-384/160, m4a3-384/192 central switch matrix block b clk0?lk3 block a block gx block hx block c block f block d block e block fx block cx block ex block dx i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix 4 4 4 oe 8 16 8 4 16 24 8 16 16 36 4 4 8 24 36 4 8 8 16 16 4 4 16 16 oe 8 24 36 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 36 24 16 16 8 16 8 4 16 oe 4 4 36 24 16 16 8 16 16 4 8 8 oe 4 4 36 24 16 16 8 16 16 4 8 8 4 4 8 36 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 36 4 4 oe i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix oe 8 16 8 4 16 24 8 16 16 36 4 4 8 24 36 4 8 8 16 16 4 4 16 16 oe 8 24 36 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 36 24 16 16 8 16 8 4 16 oe 4 4 36 24 16 16 8 16 16 4 8 8 oe 4 4 36 24 16 16 8 16 16 4 8 8 4 4 8 36 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 36 4 4 oe block g block j block h block i block bx block o block ax block p detail a repeat detail a block l block k block m block n 17466g-067
ispmach 4a family 35 block diagram - m4a3-512/160, m4a3-512/192, m4a3-512/256 central switch matrix block b clk0?lk3 block a block ox block px block c block f block d block e block nx block kx block mx block lx i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix oe 8 16 8 4 16 24 8 16 16 36 4 4 8 24 36 4 8 8 16 16 4 4 16 16 oe 8 24 36 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 36 24 16 16 8 16 8 4 16 oe 4 4 36 24 16 16 8 16 16 4 8 8 oe 4 4 36 24 16 16 8 16 16 4 8 8 4 4 8 36 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 36 4 4 oe i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 72 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix oe 8 16 8 4 16 24 8 16 16 36 4 4 8 24 36 4 8 8 16 16 4 4 16 16 oe 8 24 36 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 36 24 16 16 8 16 8 4 16 oe 4 4 36 24 16 16 8 16 16 4 8 8 oe 4 4 36 24 16 16 8 16 16 4 8 8 4 4 8 36 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 36 4 4 oe block g block j block h block i block jx block gx block ix block hx block k block n block l block m block fx block cx block ex block dx detail a repeat detail a repeat detail a block p block o block ax block bx 4 4 4 17466g-068
36 ispmach 4a family absolute maximum ratings m4a5 storage temperature . . . . . . . . . . . . . . . . . . . -65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . . . . . . . . -55 c to +100 c device junction temperature. . . . . . . . . . . . . . . . . . . . +130 c supply voltage with respect to ground . . . . . . . . . . . . . . . . .-0.5 v to +7.0 v dc input voltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . . . . . . . . 2000 v latchup current (t a = -40 c to +85 c) . . . . . . . . . . 200 ma stresses above those listed under absolute maximum r atings may cause per- manent device failure. functionality at or above these limits is not implied. expo- sure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c supply voltage (v cc ) with respect to ground. . . . . . . . . . . . . . +4.75 v to +5.25 v industrial (i) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . .-40 c to +85 c supply voltage (v cc ) with respect to ground. . . . . . . . . . . . . . . +4.50 v to +5.5 v operating ranges define those limits between which the functionality of the device is guaranteed. notes: 1. total i ol for one pal block should not exceed 64 ma. 2. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 5-v dc characteristics over operating ranges parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = ?.2 ma, v cc = min, v in = v ih or v il 2.4 v i oh = -100 ?, v cc = max, v in = v ih or v il 3.3 3.6 v v ol output low voltage i ol = 24 ma, v cc = min, v in = v ih or v il (note 1) 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 2) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 2) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 a i il input low leakage current v in = 0 v, v cc = max (note 3) ?0 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max, v in = v ih or v il (note 3) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max , v in = v ih or v il (note 3) ?0 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) ?0 ?60 ma
ispmach 4a family 37 absolute maximum ratings m4a3 storage temperature . . . . . . . . . . . . . . . . . . . -65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . . . . . . . . -55 c to +100 c device junction temperature. . . . . . . . . . . . . . . . . . . . +130 c supply voltage with respect to ground . . . . . . . . . . . . . . . . .-0.5 v to +4.5 v dc input voltage . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to 6.0 v static discharge voltage . . . . . . . . . . . . . . . . . . . . . . . . 2000 v latchup current (t a = -40 c to +85 c) . . . . . . . . . . 200 ma stresses above those listed under absolute maximum r atings may cause per- manent device failure. functionality at or above these limits is not implied. expo- sure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c supply voltage (v cc ) with respect to ground. . . . . . . . . . . . . . . . +3.0 v to +3.6 v industrial (i) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . .-40 c to +85 c supply voltage (v cc ) with respect to ground. . . . . . . . . . . . . . . . +3.0 v to +3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. notes: 1. total i ol for one pal block should not exceed 64 ma. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. notes: 1. see ?mach switching test circuit? document on the literature download page of the lattice web site. 2. this parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 3.3-v dc characteristics over operating ranges parameter symbol parameter description test conditions min typ max unit v oh output high voltage v cc = min v in = v ih or v il i oh = ?00 av cc ?0.2 v i oh = ?.2 ma 2.4 v v ol output low voltage v cc = min v in = v ih or v il (note 1) i ol = 100 a 0.2 v i ol = 24 ma 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs 2.0 5.5 v v il input low voltage guaranteed input logical low voltage for all inputs ?.3 0.8 v i ih input high leakage current v in = 3.6 v, v cc = max (note 2) 5 a i il input low leakage current v in = 0 v, v cc = max (note 2) ? a i ozh off-state output leakage current high v out = 3.6 v, v cc = max v in = v ih or v il (note 2) 5 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) ? a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) ?5 ?60 ma
38 ispmach 4a family ispmach 4a timing parameters over operating ranges 1 -5 -55 -6 -65 -7 -10 -12 -14 unit min max min max min max min max min max min max min max min max combinatorial delay: t pdi internal combinatorial propagation delay 3.5 4.0 4.3 4.5 5.0 7.0 9.0 11.0 ns t pd combinatorial propagation delay 5.0 5.5 6.0 6.5 7.5 10.0 12.0 14.0 ns registered delays: t ss synchronous clock setup time, d-type register 3.0 3.5 3.5 3.5 5.0 5.5 7.0 10.0 ns t sst synchronous clock setup time, t-type register 4.0 4.0 4.0 4.0 6.0 6.5 8.0 11.0 ns t sa asynchronous clock setup time, d-type register 2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns t sat asynchronous clock setup time, t-type register 3.0 3.0 3.0 3.5 4.5 5.0 6.0 9.0 ns t hs synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t ha asynchronous clock hold time 2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns t cosi synchronous clock to internal output 2.5 2.5 2.8 3.0 3.0 3.0 3.5 3.5 ns t cos synchronous clock to output 4.0 4.0 4.5 5.0 5.5 6.0 6.5 6.5 ns t coai asynchronous clock to internal output 5.0 5.0 5.0 5.0 6.0 8.0 10.0 12.0 ns t coa asynchronous clock to output 6.5 6.5 6.8 7.0 8.5 11.0 13.0 15.0 ns latched delays: t ssl synchronous latch setup time 4.0 4.0 4.0 4.5 6.0 7.0 8.0 10.0 ns t sal asynchronous latch setup time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns t hsl synchronous latch hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t hal asynchronous latch hold time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns t pdli transparent latch to internal output 5.5 5.5 5.8 6.0 7.5 9.0 11.0 12.0 ns t pdl propagation delay through transparent latch to output 7.0 7.0 7.5 8.0 10.0 12.0 14.0 15.0 ns t gosi synchronous gate to internal output 3.0 3.0 3.0 3.0 3.5 4.5 7.0 8.0 ns t gos synchronous gate to output 4.5 4.5 4.8 5.0 6.0 7.5 10.0 11.0 ns t goai asynchronous gate to internal output 6.0 6.0 6.0 6.0 8.5 10.0 13.0 15.0 ns t goa asynchronous gate to output 7.5 7.5 7.8 8.0 11.0 13.0 16.0 18.0 ns input register delays: t sirs input register setup time 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns t hirs input register hold time 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 ns t icosi input register clock to internal feedback 3.0 3.0 3.0 3.0 3.5 4.5 6.0 6.0 ns input latch delays: t sil input latch setup time 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 ns t hil input latch hold time 2.5 2.5 2.5 3.0 3.0 3.0 3.0 4.0 ns t igosi input latch gate to internal feedback 3.5 3.5 3.8 4.0 4.0 4.0 4.0 5.0 ns t pdili transparent input latch to internal feedback 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns
ispmach 4a family 39 input register delays with zht option: t sirz input register setup time - zht 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns t hirz input register hold time - zht 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns input latch delays with zht option: t silz input latch setup time - zht 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns t hilz input latch hold time - zht 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t pdil zi transparent input latch to internal feedback - zht 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns output delays: t buf output buffer delay 1.5 1.5 1.8 2.0 2.5 3.0 3.0 3.0 ns t slw slow slew rate delay adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ea output enable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns t er output disable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns power delay: t pl power-down mode delay adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns reset and preset delays: t sri asynchronous reset or preset to internal register output 7.5 7.7 8.0 8.0 9.5 11.0 13.0 16.0 ns t sr asynchronous reset or preset to register output 9.0 9.2 10.0 10.0 12.0 14.0 16.0 19.0 ns t srr asynchronous reset and preset register recovery time 7.0 7.0 7.5 7.5 8.0 8.0 10.0 15.0 ns t srw asynchronous reset or preset width 7.0 7.0 8.0 8.0 10.0 10.0 12.0 15.0 ns clock/le width: t wls global clock width low 2.0 2.0 2.5 2.5 3.0 4.0 5.0 6.0 ns t whs global clock width high 2.0 2.0 2.5 2.5 3.0 4.0 5.0 6.0 ns t wla product term clock width low 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns t wha product term clock width high 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns t gws global gate width low (for low transparent) or high (for high transparent) 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns t gwa product term gate width low (for low transparent) or high (for high transparent) 4.0 4.0 4.5 4.5 5.0 5.0 6.0 9.0 ns t wirl input register clock width low 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns t wirh input register clock width high 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns t wil input latch gate width 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns ispmach 4a timing parameters over operating ranges 1 -5 -55 -6 -65 -7 -10 -12 -14 unit min max min max min max min max min max min max min max min max
40 ispmach 4a family notes: 1. see ?switching test circuit? document on the literature download page of the lattice web site. 2. this parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. capacitance 1 note: 1. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified w here this parameter may be affected. frequency: f maxs external feedback, d-type, min of 1/(t wls + t whs ) or 1/(t ss + t cos ) 143 133 125 118 95.2 87.0 74.1 60.6 mhz external feedback, t-type, min of 1/(t wls + t whs ) or 1/(t sst + t cos ) 125 125 118 111 87.0 80.0 69.0 57.1 mhz internal feedback (f cnt ), d-type, min of 1/(t wls + t whs ) or 1/(t ss + t cosi ) 182 167 160 154 125 118 95.0 74.1 mhz internal feedback (f cnt ), t-type, min of 1/(t wls + t whs ) or 1/(t sst + t cosi ) 154 154 148 143 111 105 87.0 69.0 mhz no feedback 2 , min of 1/(t wls + t whs ), 1/(t ss + t hs ) or 1/(t sst + t hs ) 250 250 200 200 154 125 100 83.3 mhz f maxa external feedback, d-type, min of 1/ (t wla + t wha ) or 1/(t sa + t coa ) 111 111 108 100 83.3 66.7 55.6 43.5 mhz external feedback, t-type, min of 1/(t wla + t wha ) or 1/(t sat + t coa ) 105 105 102 95.2 76.9 62.5 52.6 41.7 mhz internal feedback (f cnta ), d-type, min of 1/(t wla + t wha ) or 1/(t sa + t coai ) 133 133 125 125 105 83.3 66.7 50.0 mhz internal feedback (f cnta ), t-type, min of 1/(t wla + t wha ) or 1/(t sat + t coai ) 125 125 125 118 95.2 76.9 62.5 47.6 mhz no feedback 2 , min of 1/(t wla + t wha ), 1/(t sa + t ha ) or 1/(t sat + t ha ) 167 167 143 143 125 100 62.5 55.6 mhz f maxi maximum input register frequency, min of 1/(t wirh + t wirl ) or 1/(t sirs + t hirs ) 167 167 143 143 125 100 83.3 83.3 mhz parameter symbol parameter description test conditions typ unit c in input capacitance v in =2.0 v 3.3 v or 5 v, 25?, 1 mhz 6 pf c i/o output capacitance v out =2.0v 3.3 v or 5 v, 25?, 1 mhz 8 pf ispmach 4a timing parameters over operating ranges 1 -5 -55 -6 -65 -7 -10 -12 -14 unit min max min max min max min max min max min max min max min max
ispmach 4a family 41 i cc vs. frequency these curves represent the typical power consumption for a particular device at system frequency. the selected ?typical? pattern is a 16-bit up-down counter. this pattern fills the device and exercises every macrocell. maximum frequency shown uses internal feedback and a d-type register. power/speed are optimized to obtain the highest counter frequency and the lowest power. the highest frequency (lsbs) is placed in common pal blocks, which are set to high power. the lowest frequency signals (msbs) are placed in a common pal block and set to lowest power. 350 300 250 200 150 100 50 0 0 20 40 60 80 100 120 140 160 180 200 v cc = 5 v or 3.3 v, t a = 25o c i cc (ma) frequency (mhz) m4a-32/32 m4a-64/32 m4a-128/64 m4a-256/128 figure 19. ispmach 4a i cc curves at high speed mode m4a-256/160 m4a-64/64 m4a-96/48 400 m4a-512/160 m4a-192/96 m4a-384/160 250 200 150 100 50 0 0 20 40 60 80 100 120 140 160 180 200 v cc = 5 v or 3.3 v, t a = 25o c m4a-32/32 i cc (ma) frequency (mhz) m4a-64/32 m4a-128/64 m4a-256/128 figure 20. ispmach 4a i cc curves at low power mode m4a-256/160 m4a-64/64 m4a-96/48 m4a-512/160 m4a-192/96 m4a-384/160
42 ispmach 4a family 44-pin plcc connection diagram (m4a(3,5)-32/32 and m4a(3,5)-64/32) top view 44-pin plcc pin designations clk/i = clock or input gnd = ground i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out 1 44 43 42 5 4 3 2 641 40 7 8 9 10 11 12 13 14 15 16 17 23 24 25 26 19 20 21 22 18 27 28 39 38 37 36 35 34 33 32 31 30 29 i/o5 i/o6 i/o7 tdi clk0/i0 gnd tck i/o8 i/o9 i/o10 i/o11 a2 a1 a0 b0 b1 b2 b3 d3 d2 d1 d0 c0 c1 c2 b3 b2 b1 b0 b8 b9 b10 a2 a1 a0 a8 a9 a10 a11 i/o27 i/o26 i/o25 i/o24 tdo gnd clk1/i1 tms i/o23 i/o22 i/o21 i/o12 i/o13 i/o14 i/o15 vcc gnd i/o16 i/o17 i/o18 i/o19 i/o20 b4 b5 b6 b7 c7 c6 c5 c4 c3 a12 a13 a14 a15 b15 b14 b13 b12 b11 i/o4 i/o3 i/o2 i/o1 i/o0 gnd vcc i/o31 i/o30 i/o29 i/o28 a3 a4 a5 a6 a7 d7 d6 d5 d4 a3 a4 a5 a6 a7 b7 b6 b5 b4 m4a(3,5)-32/32 m4a(3,5)-32/32 m4a(3,5)-64/32 m4a(3,5)-64/32 m4a(3,5)-64/32 m4a(3,5)-64/32 17466g-026 i/o cell pal block c7
ispmach 4a family 43 44-pin tqfp connection diagram (m4a(3,5)-32/32 and m4a(3,5)-64/32) top view 44-pin tqfp (1.0mm thickness) pin designations clk/i = clock or input gnd = ground i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out i/o12 i/o13 i/o14 i/o15 vcc gnd i/o16 i/o17 i/o18 i/o19 i/o20 b4 b5 b6 b7 c7 c6 c5 c4 c3 a12 a13 a14 a15 b15 b14 b13 b12 b11 i/o4 i/o3 i/o2 i/o1 i/o0 gnd vcc i/o31 i/o30 i/o29 i/o28 a3 a4 a5 a6 a7 d7 d6 d5 d4 a3 a4 a5 a6 a7 b7 b6 b5 b4 i/o27 i/o26 i/o25 i/o24 tdo gnd clk1/i1 tms i/o23 i/o22 i/o21 d3 d2 d1 d0 c0 c1 c2 b3 b2 b1 b0 b8 b9 b10 i/o5 i/o6 i/o7 tdi clk0/i0 gnd tck i/o8 i/o9 i/o10 i/o11 a2 a1 a0 b0 b1 b2 b3 a2 a1 a0 a8 a9 a10 a11 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 m4a(3,5)-32/32 m4a(3,5)-32/32 m4a(3,5)-64/32 m4a(3,5)-64/32 m4a(3,5)-64/32 m4a(3,5)-64/32 i/o cell pal block c7
44 ispmach 4a family 48-pin tqfp connection diagram (m4a(3,5)-32/32 and m4a(3,5)-64/32) top view 48-pin tqfp (1.4mm thickness) pin designations clk/i = clock or input gnd = ground i/o = input/output v cc = supply voltage nc = no connect tdi = test data in tck = test clock tms = test mode select tdo = test data out i/o12 i/o13 i/o14 i/o15 vcc nc gnd i/o16 i/o17 i/o18 i/o19 i/o20 b4 b5 b6 b7 c7 c6 c5 c4 c3 a12 a13 a14 a15 b15 b14 b13 b12 b11 i/o4 i/o3 i/o2 i/o1 i/o0 gnd nc vcc i/o31 i/o30 i/o29 i/o28 a3 a4 a5 a6 a7 d7 d6 d5 d4 a3 a4 a5 a6 a7 b7 b6 b5 b4 i/o27 i/o26 i/o25 i/o24 tdo gnd nc clk1/i1 tms i/o23 i/o22 i/o21 d3 d2 d1 d0 c0 c1 c2 b3 b2 b1 b0 b8 b9 b10 i/o5 i/o6 i/o7 tdi clk0/i0 nc gnd tck i/o8 i/o9 i/o10 i/o11 a2 a1 a0 b0 b1 b2 b3 a2 a1 a0 a8 a9 a10 a11 1 2 3 4 5 6 7 8 9 10 11 12 33 34 35 36 32 31 30 29 28 27 26 25 44 45 46 47 48 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 m4a(3,5)-32/32 m4a(3,5)-32/32 m4a(3,5)-64/32 m4a(3,5)-64/32 m4a(3,5)-64/32 m4a(3,5)-64/32 i/o cell pal block c7 17466g-028
ispmach 4a family 45 100-pin tqfp connection diagram (m4a(3,5)-96/48) top view 100-pin tqfp pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage nc = no connect tdi = test data in tck = test clock tms = test mode select tdo = test data out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 nc tdi nc nc i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i0/clk0 v cc gnd i1/clk1 i/o12 i/o13 i/o14 i/o15 i/o16 i/o17 nc nc tms tck nc a1 a0 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gnd nc nc i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 nc i2 nc nc gnd v cc i3 i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 nc nc gnd c2 c3 c4 c5 c6 c7 d7 d6 d5 d4 d3 d2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 gnd nc nc i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 i7 v cc gnd nc nc i6 nc i/o47 i/o46 i/o45 i/o44 i/o43 i/o42 nc nc gnd a2 a3 a4 a5 a6 a7 f7 f6 f5 f4 f3 f2 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc tdo nc nc nc i/o41 i/o40 i/o39 i/o38 i/o37 i/o36 i5/clk3 gnd v cc i4/clk2 i/o35 i/o34 i/o33 i/o32 i/o31 i/o30 nc nc nc nc f1 f0 e0 e1 e2 e3 e4 e5 e6 e7 d0 d1 17466g-029 i/o cell pal block c7
46 ispmach 4a family 100-pin pqfp connection diagram (m4a(3,5)-128/64) top view 100-pin pqfp pin designations i/clk = input or clock gnd = ground i = input i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out trst = test reset enable = program i/o7 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 v cc gnd gnd v cc i/o63 i/o62 i/o61 i/o60 i/o59 i/o58 i/o57 i/o56 h0 h1 h2 h3 h4 h5 h6 h7 gnd gnd tdi i5 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 io/clk0 gnd gnd i1/clk1 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 b7 b6 b5 b4 b3 b2 b1 b0 c0 c1 c2 c3 c4 c5 c6 c7 tms tck gnd gnd 28 29 30 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 2 3 99 98 100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 81 83 i/o46 i/o45 i/o44 i/o43 i/o42 i/o41 i/o40 i2 enable gnd gnd gnd td0 trst i/o55 i/o54 i/o53 i/o52 i/o51 i/o50 i/o49 i/o48 g7 g6 g5 g4 g3 g2 g1 g0 i4/clk3 gnd gnd i3/clk2 i/o47 f1 f2 f3 f4 f5 f6 f7 f0 gnd 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 gnd gnd i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 e0 e1 e2 e3 e4 e5 e6 e7 v cc v cc v cc v cc v cc v cc i/o cell pal block c7 17466g-031
ispmach 4a family 47 100-pin tqfp connection diagram (m4a3-64/64 and m4a(3,5)-128/64) top view 100-pin tqfp pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out trst = test reset enable = program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 gnd tdi i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i0/clk0 v cc gnd i1/clk1 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 tms tck gnd a1 a3 a5 a7 a9 a11 a13 a15 b15 b13 b11 b9 b7 b5 b3 b1 b7 b6 b5 b4 b3 b2 b1 b0 c0 c1 c2 c3 c4 c5 c6 c7 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gnd gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i2 v cc gnd gnd v cc i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 gnd gnd b14 b12 b10 b8 b6 b4 b2 b0 c0 c2 c4 c6 c8 c10 c12 c14 d7 d6 d5 d4 d3 d2 d1 d0 e0 e1 e2 e3 e4 e5 e6 e7 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 gnd gnd i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 v cc gnd gnd v cc i5 i/o63 i/o62 i/o61 i/o60 i/o59 i/o58 i/o57 i/o56 gnd gnd a14 a12 a10 a8 a6 a4 a2 a0 d0 d2 d4 d6 d8 d10 d12 d14 a7 a6 a5 a4 a3 a2 a1 a0 h0 h1 h2 h3 h4 h5 h6 h7 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 gnd tdo trst i/o55 i/o54 i/o53 i/o52 i/o51 i/o50 i/o49 i/o48 i4/clk3 gnd v cc i3/clk2 i/o47 i/o46 i/o45 i/o44 i/o43 i/o42 i/o41 i/o40 enable gnd d1 d3 d5 d7 d9 d11 d13 d15 c15 c13 c11 c9 c7 c5 c3 c1 g7 g6 g5 g4 g3 g2 g1 g0 f0 f1 f2 f3 f4 f5 f6 f7 m4a3-64/64 m4a3-128/64 m4a5-128/64 17466g-032a i/o cell pal block c7
48 ispmach 4a family 100-ball cabga connection diagram (m4a3-128/64) bottom view 100-ball cabga 10987654321 a gnd i/o63 h7 i/o60 h4 i/o57 h1 gnd gnd i/o1 a1 i/o4 a4 i/o7 a7 gnd a b trst gnd i/o61 h5 i5 vcc i/o0 a0 i/o6 a6 gnd tdi i/o15 b7 b c i/o53 g5 tdo i/o62 h6 i/o58 h2 i/o56 h0 i/o2 a2 gnd i/o14 b6 i/o13 b5 i/o12 b4 c d i/o50 g2 i/o55 g7 gnd i/o59 h3 i/o3 a3 i/o5 a5 i/o11 b3 i/o10 b2 clk0/i0 clk3/i4 i/o9 b1 d e i/o49 g1 i/o51 g3 i/o54 g6 vcc i/o16 c0 i/o20 c4 i/o8 b0 vcc gnd e f gnd vcc i/o40 f0 i/o52 g4 i/o48 g0 vcc i/o22 c6 i/o19 c3 i/o17 c1 clk1/i1 f g i/o41 f1 clk2/i3 i/o42 f2 i/o43 f3 i/o37 e5 i/o35 e3 i/o27 d3 gnd i/o23 c7 i/o18 c2 g h i/o44 f4 i/o45 f5 i/o46 f6 gnd i/o34 e2 i/o24 d0 i/o26 d2 i/o30 d6 tck i/o21 c5 h j i/o47 f7 enable gnd i/o38 e6 i/o32 e0 vcc i2 i/o29 d5 gnd tms j k gnd i/o39 e7 i/o36 e4 i/o33 e1 gnd gnd i/o25 d1 i/o28 d4 i/o31 d7 gnd k 10987654321 pin designations clk gnd i i/o n/c vcc tdi tck tms tdo trst enable = = = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out test reset program c7 17466g-100cabga
ispmach 4a family 49 144-pin tqfp connection diagram (m4a(3,5)-192/96) top view 144-pin tqfp pin designations clk = clock gnd = ground i = input i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out 17466g-033 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd tdi i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i2 i3 v cc gnd i4 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 gnd v cc i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 tms tck gnd d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 e7 e6 e5 e4 e3 e2 e1 e0 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i5 i6 i7 clk1 gnd v cc clk2 i8 i9 i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 v cc gnd i/o40 i/o41 i/o42 i/o43 i/o44 i/o45 i/o46 i/o47 f7 f6 f5 f4 f3 f2 f1 f0 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 i/o95 i/o94 i/o93 i/o92 i/o91 i/o90 i/o89 i/o88 gnd v cc i/o87 i/o86 i/o85 i/o84 i/o83 i/o82 i/o81 i/o80 i1 i0 clk0 gnd v cc clk3 i15 i14 i13 i/o79 i/o78 i/o77 i/o76 i/o75 i/o74 i/o73 i/o72 gnd b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 l0 l1 l2 l3 l4 l5 l6 l7 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 gnd tdo nc i/o71 i/o70 i/o69 i/o68 i/o67 i/o66 i/o65 i/o64 i12 v cc gnd i11 i10 i/o63 i/o62 i/o61 i/o60 i/o59 i/o58 i/o57 i/o56 gnd v cc i/o55 i/o54 i/o53 i/o52 i/o51 i/o50 i/o49 i/o48 nc gnd k0 k1 k2 k3 k4 k5 k6 k7 j0 j1 j2 j3 j4 j5 j6 j7 i0 i1 i2 i3 i4 i5 i6 i7 i/o cell pal block c7
50 ispmach 4a family 144-ball fpbga connection diagram (m4a3-192/96) bottom view 144-ball fpbga 121110987654321 a gnd i/o72 l7 i/o76 l3 i13 gbclk3 i0 i/o82 a2 i/o86 a6 i/o88 b0 i/o93 b5 i/o95 b7 gnd a b gnd i/o73 l6 i/o77 l2 i/o79 l0 vcc i1 i/o83 a3 i/o87 a7 i/o90 b2 i/o94 b6 i/o0 d7 tdi b c gnd tdo i/o74 l5 i14 gnd i/o80 a0 i/o84 a4 gnd i/o92 b4 i/o1 d6 i/o4 d3 i/o3 d4 c d i/o67 k4 i/o69 k2 i/o71 k0 i/o75 l4 gbclk0 i/o81 a1 vcc i/o91 b3 i/o2 d5 i2 i/o6 d1 i/o7 d0 d e i12 i/o64 k7 i/o66 k5 i/o70 k1 i/o78 l1 i/o85 a5 i/o89 b1 i/o5 d2 i/o8 c7 i4 gnd vcc e f i10 i11 gnd i/065 k6 i/o68 k3 i15 i3 gnd i/o12 c3 i/o11 c4 i/o10 c5 i/o9 c6 f g i/o60 j3 i/o61 j2 i/o62 j1 i/o63 j0 vcc gnd i7 i/o20 e3 i/o17 e6 i/o15 c0 i/o14 c1 i/o13 c2 g h i/o56 j7 i/o57 j6 i/o58 j5 i/o59 j4 i/o53 i2 i/o41 h1 i/o37 g5 i/o30 f1 i/o22 e1 i/o18 e5 i/o16 e7 vcc h j i/o55 i0 i/o54 i1 vcc i/o50 i5 i/o43 h3 vcc i/o33 g1 gbclk2 i/o27 f4 i/o23 e0 i/o21 e2 i/o19 e4 j k i/o51 i4 i/o52 i3 i/o49 i6 i/o44 h4 gnd i/o36 g4 i/o32 g0 vcc i6 i/o26 f5 tck tms k l gnd i/o48 i7 i/o46 h6 i/o42 h2 i/o39 g7 i/o35 g3 i9 gnd i/o31 f0 i/o29 f2 i/o25 f6 gnd l m gnd i/o47 h7 i/o45 h5 i/o40 h0 i/o38 g6 i/o34 g2 i8 gbclk1 i5 i/o28 f3 i/o24 f7 gnd m 121110987654321 pin designations clk gnd i i/o n/c vcc tdi tck tms tdo = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out c7 m4a3.192.96_144bga
ispmach 4a family 51 208-pin pqfp connection diagram (m4a(3,5)-256/128 and m4a3-256/160) top view 208-pin pqfp c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 gnd tdi i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 vcc gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i2 i3 gnd vcc vcc gnd gnd vcc vcc gnd i4 i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 gnd vcc i/o40 i/o41 i/o42 i/o43 i/o44 i/o45 i/o46 i/o47 tms tck gnd gnd i/o48 i/o49 i/o50 i/o51 i/o52 i/o53 i/o54 i/o55 gnd vcc i/o56 i/o57 i/o58 i/o59 i/o60 i/o61 i/o62 i/o63 i5 i6 clk1 vcc gnd gnd vcc vcc gnd gnd vcc clk2 i7 i8 i/o64 i/o65 i/o66 i/o67 i/o68 i/o69 i/o70 i/o71 vcc gnd i/o72 i/o73 i/o74 i/o75 i/o76 i/o77 i/o78 i/o79 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 g7 g6 g5 g4 g3 g2 g1 g0 h7 h6 h5 h4 h3 h2 h1 h0 i0 i1 i2 i3 i4 i5 i6 i7 j0 j1 j2 j3 j4 j5 j6 j7 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 n7 n6 n5 n4 n3 n2 n1 n0 m7 m6 m5 m4 m3 m2 m1 m0 l0 l1 l2 l3 l4 l5 l6 l7 k0 k1 k2 k3 k4 k5 k6 k7 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 p0 p1 p2 p3 p4 p5 p6 p7 o0 o1 o2 o3 o4 o5 o6 o7 gnd i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 gnd vcc i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 i1 i0 clk0 vcc gnd gnd vcc vcc gnd gnd vcc clk3 i13 i12 i/o127 i/o126 i/o125 i/o124 i/o123 i/o122 i/o121 i/o120 vcc gnd i/o119 i/o118 i/o117 i/o116 i/o115 i/o114 i/o113 i/o112 gnd gnd tdo trst i/o111 i/o110 i/o109 i/o108 i/o107 i/o106 i/o105 i/o104 vcc gnd i/o103 i/o102 i/o101 i/o100 i/o99 i/o98 i/o97 i/o96 i11 gnd vcc vcc gnd gnd vcc vcc gnd i10 i9 i/o95 i/o94 i/o93 i/o92 i/o91 i/o90 i/o89 i/o88 gnd vcc i/o87 i/o86 i/o85 i/o84 i/o83 i/o82 i/o81 i/o80 enable gnd 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 recommend to tie to vcc m4a(3, 5)- 256/128 recommend to tie to gnd pin designations clk gnd i i/o n/c vcc tdi tck tms tdo trst enable = = = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out test reset program c7 m4a3-256/160 gnd tdi i/o20 i/o21 i/o22 i/o23 i/o24 i/o25 i/o26 i/o27 vcc gnd i/o28 i/o29 i/o30 i/o31 i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 gnd vcc i/o38 i/o39 i/o40 i/o41 i/o42 gnd i/o43 i/o44 i/o45 i/o46 i/o47 i/o48 i/o49 i/o50 i/o51 gnd vcc i/o52 i/o53 i/o54 i/o55 i/o56 i/o57 i/o58 i/o59 tms tck gnd c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 d14 d12 d6 d4 e0 e2 e6 e10 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 gnd tdo nc i/o139 i/o138 i/o137 i/o136 i/o135 i/o134 i/o133 i/o132 vcc gnd i/o131 i/o130 i/o129 i/o128 i/o127 i/o126 i/o125 i/o124 i/o123 gnd i/o122 i/o121 i/o120 i/o119 i/o118 vcc gnd i/o117 i/o116 i/o115 i/o114 i/o113 i/o112 i/o111 i/o110 i/o109 i/o108 gnd vcc i/o107 i/o106 i/o105 i/o104 i/o103 i/o102 i/o101 i/o100 nc gnd n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 m10 m6 m2 m0 l4 l6 l12 l14 k0 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 k13 k14 k15 gnd i/o60 i/o61 i/o62 i/o63 i/o64 i/o65 i/o66 i/o67 gnd vcc i/o68 i/o69 i/o70 i/o71 i/o72 i/o73 i/o74 i/o75 i/o76 i/o77 clk1 vcc gnd i/o78 i/o79 i/o80 i/o81 gnd vcc clk2 i/o82 i/o83 i/o84 i/o85 i/o86 i/o87 i/o88 i/o89 i/o90 i/o91 vcc gnd i/o92 i/o93 i/o94 i/o95 i/o96 i/o97 i/o98 i/o99 gnd g15 g14 g13 g12 g11 g10 g9 g8 g7 g6 g5 g4 g3 g2 g1 g0 h14 h12 h6 h4 i4 i6 i12 i14 j0 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 j13 j14 j15 gnd i/o19 i/o18 i/o17 i/o16 i/o15 i/o14 i/o13 i/o12 gnd vcc i/o11 i/o10 i/o9 i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 clk0 vcc gnd i/o1 i/o0 i/o159 i/o158 gnd vcc clk3 i/o157 i/o156 i/o155 i/o154 i/o153 i/o152 i/o151 i/o150 i/o149 i/o148 vcc gnd i/o147 i/o146 i/o145 i/o144 i/o143 i/o142 i/o141 i/o140 gnd b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a14 a12 a6 a4 p4 p6 p12 p14 o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 o12 o13 o14 o15 17466g-044
52 ispmach 4a family 208-pin pqfp connection diagram (m4a3-384/160 and m4a3-512/160) top view 208-pin pqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 m4a3-512/160 pin designations clk gnd i i/o n/c vcc tdi tck tms tdo = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out c7 gnd tdo nc i/o137 i/o136 i/o135 i/o134 i/o133 i/o132 i/o131 i/o130 vcc gnd i/o129 i/o128 i/o127 i/o126 i/o125 i/o124 i/o123 i/o122 i/o121 gnd i/o120 i/o119 i/o118 i/o117 i/o116 vcc gnd i/o115 i/o114 i/o113 i/o112 i/o111 i/o110 i/o109 i/o108 i/o107 i/o106 gnd vcc i/o105 i/o104 i/o103 i/o102 i/o101 i/o100 i/o99 i/o98 nc gnd gnd i/o17 i/o16 i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 gnd vcc i/o9 i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 clk0 vcc gnd i/o159 i/o158 i/o157 i/o156 gnd vcc clk3 i/o155 i/o154 i/o153 i/o152 i/o151 i/o150 i/o149 i/o148 i/o147 i/o146 vcc gnd i/o145 i/o144 i/o143 i/o142 i/o141 i/o140 i/o139 i/o138 gnd gnd i/o58 i/o59 i/o60 i/o61 i/o62 i/o63 i/o64 i/o65 gnd vcc i/o66 i/o67 i/o68 i/o69 i/o70 i/o71 i/o72 i/o73 i/o74 i/o75 clk1 vcc gnd i/o76 i/o77 i/o78 i/o79 gnd vcc clk2 i/o80 i/o81 i/o82 i/o83 i/o84 i/o85 i/o86 i/o87 i/o88 i/o89 vcc gnd i/o90 i/o91 i/o92 i/o93 i/o94 i/o95 i/o96 i/o97 gnd gnd tdi i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 i/o24 i/o25 vcc gnd i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i/o32 i/o33 i/o34 i/o35 gnd vcc i/o36 i/o37 i/o38 i/o39 i/o40 gnd i/o41 i/o42 i/o43 i/o44 i/o45 i/o46 i/o47 i/o48 i/o49 gnd vcc i/o50 i/o51 i/o52 i/o53 i/o54 i/o55 i/o56 i/o57 tms tck gnd c7 c6 c5 c4 c3 c2 c1 c0 f7 f6 f5 f4 f3 f2 f1 f0 e7 e5 e2 e0 h0 h2 h3 h5 g0 g1 g2 g3 g4 g5 g6 g7 j0 j1 j2 j3 j4 j5 j6 j7 gnd tdi i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 i/o24 i/o25 vcc gnd i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i/o32 i/o33 i/o34 i/o35 gnd vcc i/o36 i/o37 i/o38 i/o39 i/o40 gnd i/o41 i/o42 i/o43 i/o44 i/o45 i/o46 i/o47 i/o48 i/o49 gnd vcc i/o50 i/o51 i/o52 i/o53 i/o54 i/o55 i/o56 i/o57 tms tck gnd gnd i/o58 i/o59 i/o60 i/o61 i/o62 i/o63 i/o64 i/o65 gnd vcc i/o66 i/o67 i/o68 i/o69 i/o70 i/o71 i/o72 i/o73 i/o74 i/o75 clk1 vcc gnd i/o76 i/o77 i/o78 i/o79 gnd vcc clk2 i/o80 i/o81 i/o82 i/o83 i/o84 i/o85 i/o86 i/o87 i/o88 i/o89 vcc gnd i/o90 i/o91 i/o92 i/o93 i/o94 i/o95 i/o96 i/o97 gnd k7 k6 k5 k4 k3 k2 k1 k0 i7 i6 i5 i4 i3 i2 i1 i0 l7 l6 l4 l1 m1 m4 m6 m7 p0 p1 p2 p3 p4 p5 p6 p7 n0 n1 n2 n3 n4 n5 n6 n7 b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a4 a1 hx1 hx4 hx6 hx7 ex0 ex1 ex2 ex3 ex4 ex5 ex6 ex7 gx0 gx1 gx2 gx3 gx4 gx5 gx6 gx7 gnd i/o17 i/o16 i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 gnd vcc i/o9 i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 clk0 vcc gnd i/o159 i/o158 i/o157 i/o156 gnd vcc clk3 i/o155 i/o154 i/o153 i/o152 i/o151 i/o150 i/o149 i/o148 i/o147 i/o146 vcc gnd i/o145 i/o144 i/o143 i/o142 i/o141 i/o140 i/o139 i/o138 gnd m4a3-384/160 fx7 fx6 fx5 fx4 fx3 fx2 fx1 fx0 cx7 cx6 cx5 cx4 cx3 cx2 cx1 cx0 dx5 dx3 dx2 dx0 ax0 ax2 ax5 ax7 bx0 bx1 bx2 b3x bx4 bx5 bx6 bx7 o0 o1 o2 o3 o4 o5 o6 o7 gnd tdo nc i/o137 i/o136 i/o135 i/o134 i/o133 i/o132 i/o131 i/o130 vcc gnd i/o129 i/o128 i/o127 i/o126 i/o125 i/o124 i/o123 i/o122 i/o121 gnd i/o120 i/o119 i/o118 i/o117 i/o116 vcc gnd i/o115 i/o114 i/o113 i/o112 i/o111 i/o110 i/o109 i/o108 i/o107 i/o106 gnd vcc i/o105 i/o104 i/o103 i/o102 i/o101 i/o100 i/o99 i/o98 nc gnd f7 f6 f5 f4 f3 f2 f1 f0 g7 g6 g5 g4 g3 g2 g1 g0 e7 e5 e2 e0 l0 l2 l3 l5 j0 j1 j2 j3 j4 j5 j6 j7 k0 k1 k2 k3 k4 k5 k6 k7 o7 o6 o5 o4 o3 o2 o1 o0 n7 n6 n5 n4 n3 n2 n1 n0 p7 p6 p4 p1 ax1 ax4 ax6 ax7 cx0 cx1 cx2 cx3 cx4 cx5 cx6 cx7 bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 kx7 kx6 kx5 kx4 kx3 kx2 kx1 kx0 jx7 jx6 jx5 jx4 jx3 jx2 jx1 jx0 lx5 lx3 lx2 lx0 ex0 ex2 ex5 ex7 gx0 gx1 gx2 gx3 gx4 gx5 gx6 gx7 fx0 fx1 fx2 fx3 fx4 fx5 fx6 fx7 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 a7 a6 a4 a1 px1 px4 px6 px7 nx0 nx1 nx2 nx3 nx4 nx5 nx6 nx7 ox0 ox1 ox2 ox3 ox4 ox5 ox6 ox7 17466ga-044
ispmach 4a family 53 256-ball bga connection diagram (m4a3-256/128) bottom view 256-ball bga gnd gnd i/o116 o3 i/o120 p7 i/o123 p4 gnd i12 gnd n/c gnd n/c n/c gnd i1 a b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y n/c i/o113 o6 n/c i/o117 o2 i/o119 o0 i/o122 p5 i/o125 p2 i/o127 p0 n/c clk3 clk0 n/c i/o0 a0 i/o1 a1 gnd n/c vcc i/o112 o7 i/o114 o5 i/o118 o1 i/o121 p6 i/o126 p1 n/c n/c n/c n/c i/o2 a2 i/o6 a6 i/o108 n4 i/o109 n5 trst vcc tdi i/o115 o4 vcc i/o124 p3 i13 n/c n/c i0 i/o3 a3 vcc i/o105 n1 i/o106 n2 i/o111 n7 vcc gnd i/o103 m7 i/o107 n3 i/o110 n6 i/o100 m4 i/o102 m6 i/o104 n0 vcc i/o96 m0 i/o98 m2 i/o101 m5 n/c gnd n/c i/o97 m1 i/o99 m3 gnd i11 n/c n/c gnd n/c i10 i9 gnd n/c i/o94 l1 i/o92 l3 gnd i/o82 k5 vcc i/o79 j7 i/o77 j5 i/o73 j1 i/o70 i6 i/o66 i2 n/c n/c n/c n/c i/o61 h2 i/o57 h6 gnd 20 19 18 17 16 15 14 13 12 11 10 9 i/o95 l0 i/o93 l2 i/o90 l5 n/c 8 i/o91 l4 i/o89 l6 i/o86 k1 vcc 7 gnd i/o88 l7 i/o84 k3 i/o81 k6 6 i/o87 k0 i/o85 k2 i/o80 k7 vcc 5 n/c i/o83 k4 enable vcc tdo i/o76 j4 vcc i/o67 i3 i7 n/c n/c i6 i/o60 h3 vcc 43 gnd n/c i/o78 j6 i/o75 j3 i/o72 j0 i/o69 i5 i/o65 i1 i/o64 i0 n/c clk2 clk1 i/o63 h0 i/o59 h4 i/o58 h5 21 2019181716151413121110987654321 gnd i/o74 j2 i/o71 i7 i/o68 i4 gnd i8 gnd n/c n/c gnd i/o62 h1 gnd i5 gnd i/o4 a4 i/o7 a7 i/o5 a5 i/o8 b0 i/o11 b3 i/o9 b1 i/o12 b4 i/o15 b7 n/c tck vcc vcc i/o18 c5 vcc i/o24 d7 i/o29 d2 i2 n/c i/o35 e3 i/o54 g1 i/o50 g5 i/o48 g7 n/c vcc n/c vcc i/o51 g4 tms vcc i/o56 h7 i/o55 g0 i/o53 g2 gnd n/c n/c i/o10 b2 gnd gnd i/o13 b5 i/o14 b6 gnd vcc n/c gnd i/o16 c7 n/c n/c i/o17 c6 i/o19 c4 i/o20 c3 i/o21 c2 i/o22 c1 gnd i/o23 c0 i/o25 d6 i/o26 d5 i/o27 d4 i/o28 d3 i/o30 d1 i/o31 d0 n/c gnd i3 n/c gnd n/c i4 gnd i/o33 e1 n/c gnd vcc n/c gnd i/o37 e5 i/o34 e2 i/o32 e0 i/o41 f1 i/o38 e6 i/o36 e4 i/o43 f3 i/o39 e7 gnd i/o46 f6 i/o42 f2 i/o40 f0 i/o47 f7 i/o45 f5 i/o44 f4 i/o52 g3 i/o49 g6 n/c n/c gnd gnd pin designations clk gnd i i/o n/c vcc tdi tck tms tdo trst enable = = = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out test reset program c7 17466g-045
54 ispmach 4a family 256-ball fpbga connection diagram (m4a3-256/192) bottom view 256-ball fpbga pin designations clk gnd i i/o n/c vcc tdi tck tms tdo = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out c7 16151413121110987654321 a i/o167 n15 i/o181 o13 i/o180 o12 i/o177 o9 i/o174 o6 i/o172 o4 i/o191 p14 i/o186 p4 i/o1 a2 i/o3 a6 gclk0 i/o9 b1 i/o13 b5 i/o15 b7 i/o18 b10 i/o20 b12 a b i/o165 n13 i/o166 n14 i/o182 o14 i/o179 o11 i/o175 o7 i/o173 o5 i/o168 o0 i/o187 p6 i/o0 a0 i/o5 a10 i/o7 a14 i/o10 b2 i/o16 b8 i/o19 b11 i/o21 b13 nc b c i/o163 n11 i/o164 n12 nc i/o183 o15 i/o178 o10 i/o170 o2 i/o171 o3 i/o189 p10 i/o184 p0 i/o6 a12 i/o12 b4 i/o14 b6 i/o23 b15 i/o22 b14 tdi i/o39 c15 c d i/o158 n6 i/o159 n7 tdo gnd gnd vcc gnd vcc gnd gnd vcc gnd vcc i/o17 b9 i/o38 c14 i/o37 c13 d e i/o156 n4 nc i/o162 n10 vcc i/o160 n8 i/o161 n9 i/o190 p12 gclk3 i/o188 p8 i/o2 a4 i/o8 b0 nc gnd i/o36 c12 i/o35 c11 i/o31 c7 e f i/o152 n0 i/o157 n5 i/o155 n3 gnd i/o154 n2 i/o153 n1 i/o176 o8 i/o169 o1 i/o185 p2 i/o4 a8 i/o11 b3 i/o34 c10 vcc i/o32 c8 i/o30 c6 i/o29 c5 f g i/o147 m6 i/o150 m12 i/o149 m10 vcc i/o148 m8 i/o151 m14 vcc gnd gnd vcc i/o33 c9 i/o28 c4 gnd i/o26 c2 i/o25 c1 i/o47 d14 g h i/o144 m0 i/o146 m4 i/145 om2 gnd i/o136 l0 i/o137 l2 gnd vcc vcc gnd i/o27 c3 i/o24 c0 vcc i/o44 d8 i/o43 d6 i/o42 d4 h j i/o138 l4 i/o139 l6 i/o140 l8 gnd i/o142 l12 i/o141 l10 gnd vcc vcc gnd i/o46 d12 i/o45 d10 gnd i/o49 e2 i/o48 e0 i/o50 e4 j k i/o143 l14 i/o120 k0 i/o121 k1 vcc i/o123 k3 i/o122 k2 vcc gnd gnd vcc i/o41 d2 i/o40 d0 vcc i/o55 e14 i/o54 e12 i/o56 f0 k l i/o124 k4 i/o125 k5 i/o127 k7 gnd i/o130 k10 i/o126 k6 i/o98 i4 i/o91 h6 i/o75 g3 i/o77 g5 i/o52 e8 i/o51 e6 gnd i/o59 f3 i/o60 f4 i/o57 f1 l m i/o128 k8 i/o129 k9 i/o131 k11 gnd i/o107 j3 i/o105 j1 i/o100 i8 i/o90 h4 i/o74 g2 i/o80 g8 i/o83 g11 i/o53 e10 vcc i/o68 f12 i/o63 f7 i/o58 f2 m n i/o132 k12 i/o133 k13 i/o135 k15 vcc gnd vcc gnd vcc gnd gnd vcc gnd gnd tck i/o64 f8 i/o61 f5 n p i/o134 k14 i/o117 j13 i/o118 j14 i/o119 j15 i/o108 j4 i/o106 j2 i/o101 i10 i/o89 h2 i/o93 h10 i/o94 h12 i/o79 g7 i/o84 g12 i/o87 g15 tms i/o65 f9 i/o62 f6 p r i/o116 j12 i/o115 j11 i/o112 j8 i/o111 j7 i/o104 j0 i/o102 i12 i/o99 i6 i/o96 i0 i/o92 h8 i/o72 g0 i/o76 g4 i/o81 g9 i/o85 g13 i/o71 f15 i/o67 f11 i/o66 f10 r t i/o114 j10 i/o113 j9 i/o110 j6 i/o109 j5 i/o103 i14 gclk2 i/o97 i2 i/o88 h0 gclk1 i/o95 h14 i/o73 g1 i/o78 g6 i/o82 g10 i/o86 g14 i/o70 f14 i/o69 f13 t 16151413121110987654321 17466g-047
ispmach 4a family 55 256-ball bga connection diagram - (m4a3-384/192) bottom view 256-ball bga gnd gnd i/o0 gx6 i/o1 ex7 i/o2 ex0 gnd i/o3 hx6 gnd i/o4 hx0 gnd i/o5 a2 i/o6 a4 gnd i/o7 d2 a b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y i/o11 fx7 i/o12 gx7 i/o13 gx5 i/o14 gx3 i/o15 gx0 i/o16 ex1 i/o17 ex4 i/o18 hx5 i/o19 hx1 clk3 clk0 i/o20 a3 i/o21 a7 i/o22 d3 gnd i/o28 fx5 vcc i/o29 gx4 i/o30 gx1 i/o31 ex6 i/o32 ex5 i/o33 ex2 i/o34 hx4 i/o35 hx2 i/o36 a0 i/o37 a5 i/o38 d0 i/o39 d4 i/o44 fx6 i/o45 fx3 i/o46 fx4 vcc tdi i/o47 gx2 vcc i/o48 ex3 i/o49 hx7 i/o50 hx3 i/o51 a1 i/o52 a6 i/o53 d1 vcc i/o58 cx6 i/o59 cx7 i/o60 fx2 vcc gnd i/o64 cx5 i/o65 fx1 i/o66 fx0 i/o70 cx2 i/o71 cx3 i/o72 cx4 vcc i/o76 dx6 i/o77 dx7 i/o78 cx0 i/o79 cx1 gnd i/o84 dx5 i/o85 dx4 i/o86 dx3 gnd i/o90 dx2 i/o91 dx1 i/o92 dx0 gnd i/o96 ax0 i/o97 ax1 i/o98 ax2 gnd i/o102 ax3 i/o103 ax4 i/o104 ax7 gnd i/o148 o6 vcc i/o149 n4 i/o150 n2 i/o151 n0 i/o152 p4 i/o153 p1 i/o154 m5 i/o155 m1 i/o156 l4 i/o157 l5 i/o158 i0 i/o159 i4 gnd 20 19 18 17 16 15 14 13 12 11 10 9 i/o108 ax5 i/o109 ax6 i/o110 bx2 i/o111 b3x 8 i/o116 bx0 i/o117 bx1 i/o118 bx5 vcc 7 gnd i/o122 bx4 i/o123 o0 i/o124 o2 6 i/o128 bx7 i/o129 bx6 i/o130 o1 vcc 5 i/o134 o3 i/o135 o4 i/o136 o5 vcc tdo i/o137 n1 vcc i/o138 p2 i/o139 m6 i/o140 m0 i/o141 l3 i/o142 l6 i/o143 i5 vcc 43 gnd i/o164 o7 i/o165 n7 i/o166 n5 i/o167 n3 i/o168 p5 i/o169 p3 i/o170 p0 i/o171 m4 clk2 clk1 i/o172 l0 i/o173 l7 i/o174 i1 21 2019181716151413121110987654321 gnd i/o181 n6 i/o182 p7 i/o183 p6 gnd i/o184 m7 gnd i/o185 m3 i/o186 m2 gnd i/o187 l1 gnd i/o188 l2 gnd i/o8 b3 i/o9 b4 i/o23 d5 i/o24 b0 i/o25 b1 i/o40 d6 i/o41 b7 i/o42 b6 i/o54 d7 tck vcc vcc i/o67 c0 vcc i/o80 f0 i/o87 e5 i/o93 e2 i/o99 h2 i/o105 h5 i/o160 k0 i/o161 k4 i/o162 k7 i/o112 g0 vcc i/o125 j1 vcc i/o144 k5 tms vcc i/o175 i3 i/o176 k1 i/o177 k2 gnd i/o189 i2 i/o190 i6 i/o10 b5 gnd gnd i/o26 b2 i/o27 c7 gnd vcc i/o43 c6 gnd i/o55 c5 i/o56 c3 i/o57 c4 i/o61 c2 i/o62 f7 i/o63 f6 i/o68 c1 i/o69 f5 gnd i/o73 f4 i/o74 f3 i/o75 f2 i/o81 f1 i/o82 e7 i/o83 e6 i/o88 e4 i/o89 e3 gnd i/o94 e1 i/o95 e0 gnd i/o100 h1 i/o101 h0 gnd i/o106 h4 i/o107 h3 gnd vcc i/o163 j6 gnd i/o113 g1 i/o114 h7 i/o115 h6 i/o119 g4 i/o120 g3 i/o121 g2 i/o126 j0 i/o127 g5 gnd i/o131 j2 i/o132 g7 i/o133 g6 i/o145 j5 i/o146 j4 i/o147 j3 i/o178 k3 i/o179 j7 i/o180 k6 i/o191 i7 gnd gnd pin designations clk gnd i i/o n/c vcc tdi tck tms tdo = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out c7 17466g-046
56 ispmach 4a family 256-ball fpbga connection diagram (m4a3-256/128) bottom view 256-ball fpbga 16151413121110987654321 a trst i/o117 o5 i/o116 o4 i/o113 o1 i/o126 p6 i/o124 p4 i12 nc nc nc clk0 i/o1 a1 i/o5 a5 i/o7 a7 i/o10 b2 i/o12 b4 a b i/o110 n6 i/o111 n7 i/o118 o6 i/o115 o3 i/o127 p7 i/o125 p5 i/o120 p0 nc nc nc i1 i/o2 a2 i/o8 b0 i/o11 b3 i/o13 b5 nc b c i/o108 n4 i/o109 n5 nc i/o119 o7 i/o114 o2 i/o122 p2 i/o123 p3 nc nc i0 i/o4 a4 i/o6 a6 i/o14 b6 tdi i/o23 c7 c d nc i/o104 n0 tdo gnd gnd vcc gnd vcc gnd gnd vcc gnd vcc i/o9 b1 i/o22 c6 i/o21 c5 d e i/o102 m6 nc i/o107 n3 vcc i/o105 n1 i/o106 n2 i13 clk3 nc nc i/o0 a0 nc gnd i/o20 c4 i/o19 c3 i/o31 d7 e f i/o98 m2 i/o103 m7 i/o101 m5 gnd i/o100 m4 i/o99 m3 i/o112 o0 i/o121 p1 nc nc i/o3 a3 i/o18 c2 vcc i/o16 c0 i/o30 d6 i/o29 d5 f g nc i/o96 m0 i11 vcc nc i/o97 m1 vcc gnd gnd vcc i/o17 c1 i/o28 d4 gnd i/o26 d2 i/o25 d1 i2 g h i/o88 l0 i10 i9 gnd i/o89 l1 i/o90 l2 gnd vcc vcc gnd i/o27 d3 i/o24 d0 vcc nc nc nc h j i/o91 l3 i/o92 l4 i/o93 l5 gnd i/o95 l7 i/o94 l6 gnd vcc vcc gnd i3 nc gnd nc nc nc j k nc nc nc vcc nc nc vcc gnd gnd vcc nc nc vcc i4 nc i/o32 e0 k l nc nc i/o80 k0 gnd i/o83 k3 nc nc nc i/o59 h3 i/o61 h5 nc nc gnd i/o35 e3 i/o36 e4 i/o33 e1 l m i/o81 k1 i/o82 k2 i/o84 k4 gnd i/o67 i3 i/o65 i1 nc nc i/o58 h2 i/o48 g0 i/o51 g3 nc vcc i/o44 f4 i/o39 e7 i/o34 e2 m n i/o85 k5 i/o86 k6 enable vcc gnd vcc gnd vcc gnd gnd vcc gnd gnd tck i/o40 f0 i/o37 e5 n p i/o87 k7 i/o77 j5 i/o78 j6 i/o79 j7 i/o68 i4 i/o66 i2 nc nc nc i6 i/o63 h7 i/o52 g4 i/o55 g7 tms i/o41 f1 i/o38 e6 p r i/o76 j4 i/o75 j3 i/o72 j0 i/o71 i7 i/o64 i0 i7 nc nc nc i/o56 h0 i/o60 h4 i/o49 g1 i/o53 g5 i/o47 f7 i/o43 f3 i/o42 f2 r t i/o74 j2 i/o73 j1 i/o70 i6 i/o69 i5 i8 clk2 nc nc clk1 i5 i/o57 h1 i/o62 h6 i/o50 g2 i/o54 g6 i/o46 f6 i/o45 f5 t 16151413121110987654321 pin designations clk gnd i i/o n/c vcc tdi tck tms tdo trst enable = = = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out test reset program c7 i/o15 b7 m4a3.256.128_256bga
ispmach 4a family 57 256-ball fpbga connection diagram (m4a3-384/192) bottom view 256-ball fpbga 16151413121110987654321 a i/o175 fx7 i/o181 gx5 i/o180 gx4 i/o177 gx1 i/o166 ex6 i/o164 ex4 i/o191 hx7 i/o186 hx2 i/o1 a1 i/o3 a3 clk0 i/o25 d1 i/o29 d5 i/o31 d7 i/o10 b2 i/o12 b4 a b i/o173 fx5 i/o174 fx6 i/o182 gx6 i/o179 gx3 i/o167 ex7 i/o165 ex5 i/o160 ex0 i/o187 hx3 i/o0 a0 i/o5 a5 i/o7 a7 i/o26 d2 i/o8 b0 i/o11 b3 i/o13 b5 n/c b c i/o171 fx3 i/o172 fx4 n/c i/o183 gx7 i/o178 gx2 i/o162 ex2 i/o163 ex3 i/o189 hx5 i/o184 hx0 i/o6 a6 i/o28 d4 i/o30 d6 i/o15 b7 i/o14 b6 tdi i/o23 c7 c d i/o150 cx6 i/o151 cx7 tdo gnd gnd vcc gnd vcc gnd gnd vcc gnd vcc i/o9 b1 i/o22 c6 i/o21 c5 d e i/o148 cx4 n/c i/o170 fx2 vcc i/o168 fx0 169 fx1 i/o190 hx6 clk3 i/o188 hx4 i/o2 a2 i/o24 d0 n/c gnd i/o20 c4 i/o19 c3 i/o47 f7 e f i/o144 cx0 i/o149 cx5 i/o147 cx3 gnd i/o146 cx2 i/o145 cx1 i/o176 gx0 i/o161 ex1 i/o185 hx1 i/o4 a4 i/o27 d3 i/o18 c2 vcc i/o16 c0 i/o46 f6 i/o45 f5 f g i/o155 dx3 i/o158 dx6 i/o157 dx5 vcc i/o156 dx4 i/o159 dx7 vcc gnd gnd vcc i/o17 c1 i/o44 f4 gnd i/o42 f2 i/o41 f1 i/o39 e7 g h i/o152 dx0 i/o154 dx2 i/o153 dx1 gnd i/o128 ax0 i/o129 ax1 gnd vcc vcc gnd i/o43 f3 i/o40 f0 vcc i/o36 e4 i/o35 e3 i/o34 e2 h j i/o130 ax2 i/o131 ax3 i/o132 ax4 gnd i/o134 ax6 i/o133 ax5 gnd vcc vcc gnd i/o38 e6 i/o37 e5 gnd i/o57 h1 i/o56 h0 i/o58 h2 j k i/o135 ax7 i/o136 bx0 i/o137 bx1 vcc i/o139 bx3 i/o138 bx2 vcc gnd gnd vcc i/o33 e1 i/o32 e0 vcc i/o63 h7 i/o62 h6 i/o48 g0 k l i/o140 bx4 i/o141 bx5 i/o143 bx7 gnd i/o114 o2 i/o142 bx6 i/o98 m2 i/o91 l3 i/o67 i3 i/o69 i5 i/o60 h4 i/o59 h3 gnd i/o51 g3 i/o52 g4 i/o49 g1 l m i/o112 o0 i/o113 o1 i/o115 o3 gnd i/o123 p3 i/o121 p1 i/o100 m4 i/o90 l2 i/o66 i2 i/o80 k0 i/o83 k3 i/o61 h5 vcc i/o76 j4 i/o55 g7 i/o50 g2 m n i/o116 o4 i/o117 o5 i/o119 o7 vcc gnd vcc gnd vcc gnd gnd vcc gnd gnd tck i/o72 j0 i/o53 g5 n p i/o118 o6 i/o109 n5 i/o110 n6 i/o111 n7 i/o124 p4 i/o122 p2 i/o101 m5 i/o89 l1 i/o93 l5 i/o94 l6 i/o71 i7 i/o84 k4 i/o87 k7 tms i/o73 j1 i/o54 g6 p r i/o108 n4 i/o107 n3 i/o104 n0 i/o127 p7 i/o120 p0 i/o102 m6 i/o99 m3 i/o96 m0 i/o92 l4 i/o64 i0 i/o68 i4 i/o81 k1 i/o85 k5 i/o79 j7 i/o75 j3 i/o74 j2 r t i/o106 n2 i/o105 n1 i/o126 p6 i/o125 p5 i/o103 m7 clk2 i/o97 m1 i/o88 l0 clk1 i/o95 l7 i/o65 i1 i/o70 i6 i/o82 k2 i/o86 k6 i/o78 j6 i/o77 j5 t 16151413121110987654321 pin designations clk gnd i i/o n/c vcc tdi tck tms tdo = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out c7 m4a3.384.192_256bga
58 ispmach 4a family 256-ball fpbga connection diagram (m4a3-512/192) bottom view 256-ball fpbga 16151413121110987654321 a i/o159 kx7 i/o181 ox5 i/o180 ox4 i/o177 ox1 i/o174 nx6 i/o172 nx4 i/o191 px7 i/o186 px2 i/o1 a1 i/o3 a3 clk0 i/o17 c1 i/o21 c5 i/o23 c7 i/o10 b2 i/o12 b4 a b i/o157 kx5 i/o158 kx6 i/o182 ox6 i/o179 ox3 i/o175 nx7 i/o173 nx5 i/o168 nx0 i/o187 px3 i/o0 a0 i/o5 a5 i/o7 a7 i/o18 c2 i/o8 b0 i/o11 b3 i/o13 b5 n/c b c i/o155 kx3 i/o156 kx4 n/c i/o183 ox7 i/o178 ox2 i/o170 nx2 i/o171 nx3 i/o189 px5 i/o184 px0 i/o6 a6 i/o20 c4 i/o22 c6 i/o15 b7 i/o14 b6 tdi i/o39 f7 c d i/o150 jx6 i/o151 jx7 tdo gnd gnd vcc gnd vcc gnd gnd vcc gnd vcc i/o9 b1 i/o38 f6 i/o37 f5 d e i/o148 jx4 n/c i/o154 kx2 vcc i/o152 kx0 i/o153 kx1 i/o190 px6 clk3 i/o188 px4 i/o2 a2 i/o16 c0 n/c gnd i/o36 f4 i/o35 f3 i/o47 g7 e f i/o144 jx0 i/o149 jx5 i/o147 jx3 gnd i/o146 jx2 i/o145 jx1 i/o176 ox0 i/o169 nx1 i/o185 px1 i/o4 a4 i/o19 c3 i/o34 f2 vcc i/o32 f0 i/o46 g6 i/o45 g5 f g i/o163 lx3 i/o166 lx6 i/o165 lx5 vcc i/o164 lx4 i/o167 lx7 vcc gnd gnd vcc i/o33 f1 i/o44 g4 gnd i/o42 g2 i/o41 g1 i/o31 e7 g h i/o160 lx0 i/o162 lx2 i/o161 lx1 gnd i/o120 ex0 i/o121 ex1 gnd vcc vcc gnd i/o43 g3 i/o40 g0 vcc i/o28 e4 i/o27 e3 i/o26 e2 h j i/o122 ex2 i/o123 ex3 i/o124 ex4 gnd i/o126 ex6 i/o125 ex5 gnd vcc vcc gnd i/o30 e6 i/o29 e5 gnd i/o65 l1 i/o64 l0 i/o66 l2 j k i/o127 ex7 i/o136 gx0 i/o137 gx1 vcc i/o139 gx3 i/o138 gx2 vcc gnd gnd vcc i/o25 e1 i/o24 e0 vcc i/o71 l7 i/o70 l6 i/o48 j0 k l i/o140 gx4 i/o141 gx5 i/o143 gx7 gnd i/o130 fx2 i/o142 gx6 i/o98 ax2 i/o91 p3 i/o75 n3 i/o77 n5 i/o68 l4 i/o67 l3 gnd i/o51 j3 i/o52 j4 i/o49 j1 l m i/o128 fx0 i/o129 fx1 i/o131 fx3 gnd i/o115 cx3 i/o113 cx1 i/o100 ax4 i/o90 p2 i/o74 n2 i/o80 o0 i/o83 o3 i/o69 l5 vcc i/o60 k4 i/o55 j7 i/o50 j2 m n i/o132 fx4 i/o133 fx5 i/o135 fx7 vcc gnd vcc gnd vcc gnd gnd vcc gnd gnd tck i/o56 k0 i/o53 j5 n p i/o134 fx6 i/o109 bx5 i/o110 bx6 i/o111 bx7 i/o116 cx4 i/o114 cx2 i/o101 ax5 i/o89 p1 i/o93 p5 i/o94 p6 i/o79 n7 i/o84 o4 i/o87 o7 tms i/o57 k1 i/o54 j6 p r i/o108 bx4 i/o107 bx3 i/o104 bx0 i/o119 cx7 i/o112 cx0 i/o102 ax6 i/o99 ax3 i/o96 ax0 i/o92 p4 i/o72 n0 i/o76 n4 i/o81 o1 i/o85 o5 i/o63 k7 i/o59 k3 i/o58 k2 r t i/o106 bx2 i/o105 bx1 i/o118 cx6 i/o117 cx5 i/o103 ax7 clk2 i/o97 ax1 i/o88 p0 clk1 i/o95 p7 i/o73 n1 i/o78 n6 i/o82 o2 i/o86 o6 i/o62 k6 i/o61 k5 t 16151413121110987654321 pin designations clk gnd i i/o n/c vcc tdi tck tms tdo = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out c7 m4a3.512.192_256bga
ispmach 4a family 59 388-ball fpbga connection diagram (m4a3-512/256) bottom view 388-ball fpbga 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a gnd i/o243 ox3 i/o240 ox0 i/o241 ox1 i/o236 nx4 i/o231 mx7 i/o228 mx4 i/o226 mx2 i/o255 px7 i/o251 px3 i/o248 px0 i/o0 a0 i/o5 a5 i/o6 a6 i/o27 d3 i/o30 d6 i/o17 c1 i/o22 c6 i/o8 b0 i/o10 b2 n/c gnd a b n/c gnd i/o245 ox5 i/o242 ox2 i/o238 nx6 i/o234 nx2 i/o232 nx0 i/o229 mx5 i/o224 mx0 i/o253 px5 i/o249 px1 i/o2 a2 clk0 i/o26 d2 i/o29 d5 i/o31 d7 i/o20 c4 i/o9 b1 i/o12 b4 i/o13 b5 gnd tdi b c i/o213 kx5 tdo gnd i/o247 ox7 i/o244 ox4 i/o239 nx7 i/o235 nx3 i/o230 mx6 i/o227 mx3 clk3 i/o250 px2 i/o1 a1 i/o7 a7 i/o25 d1 i/o16 c0 i/o18 c2 i/o23 c7 i/o11 b3 i/o15 b7 gnd i/o47 f7 i/o44 f4 c d i/o210 kx2 i/o212 kx4 i/o215 kx7 gnd i/o246 ox6 vcc i/o237 nx5 i/o233 nx1 vcc i/o254 px6 vcc i/o3 a3 i/o24 d0 vcc i/o19 c3 i/o21 c5 vcc i/o14 b6 gnd i/o46 f6 i/o43 f3 i/o41 f1 d e i/o207 jx7 i/o209 kx1 i/o211 kx3 i/o214 kx6 i/o45 f5 i/o42 f2 i/o40 f0 i/o54 g6 e f i/o203 jx3 i/o205 jx5 i/o208 kx0 vcc vcc i/o55 g7 i/o52 g4 i/o50 g2 f g i/o200 jx0 i/o202 jx2 i/o204 jx4 i/o206 jx6 vcc vcc n/c i/o225 mx1 i/o252 px4 i/o4 a4 i/o28 d4 n/c vcc vcc i/o53 g5 i/o51 g3 i/o49 g1 i/o39 e7 g h i/o221 lx5 i/o222 lx6 i/o223 lx7 i/o201 jx1 vcc n/c gnd gnd gnd gnd gnd gnd n/c vcc i/o48 g0 i/o38 e6 i/o37 e5 i/o36 e4 h j i/o218 lx2 i/o219 lx3 i/o220 lx4 vcc n/c gnd gnd gnd gnd gnd gnd gnd gnd n/c vcc i/o35 e3 i/o34 e2 i/o32 e0 j k i/o197 ix5 i/o198 ix6 i/o199 ix7 i/o216 lx0 i/o217 lx1 gnd gnd gnd gnd gnd gnd gnd gnd i/o33 e1 i/o63 h7 i/o62 h6 i/o61 h5 i/o60 h4 k l i/o192 ix0 i/o194 ix2 i/o195 ix3 i/o196 ix4 i/o193 ix1 gnd gnd gnd gnd gnd gnd gnd gnd i/o58 h2 vcc i/o59 h3 i/o57 h1 i/o56 h0 l m i/o184 hx0 i/o185 hx1 i/o187 hx3 vcc i/o186 hx2 gnd gnd gnd gnd gnd gnd gnd gnd i/o69 i5 i/o67 i3 i/o65 i1 i/o66 i2 i/o64 i0 m n i/o188 hx4 i/o189 hx5 i/o191 hx7 i/o190 hx6 i/o162 ex2 gnd gnd gnd gnd gnd gnd gnd gnd i/o89 l1 i/o88 l0 i/o71 i7 i/o70 i6 i/o68 i4 n p i/o160 ex0 i/o161 ex1 i/o163 ex3 vcc n/c gnd gnd gnd gnd gnd gnd gnd gnd n/c vcc i/o92 l4 i/o91 l3 i/o90 l2 p r i/o164 ex4 i/o165 ex5 i/o166 ex6 i/o177 gx1 vcc n/c gnd gnd gnd gnd gnd gnd n/c vcc i/o74 j2 i/o95 l7 i/o94 l6 i/o93 l5 r t i/o167 ex7 i/o176 gx0 i/o179 gx3 i/o181 gx5 vcc vcc n/c i/o152 dx0 i/o131 ax3 i/o122 p2 i/o98 m2 n/c vcc vcc i/o78 j6 i/o76 j4 i/o73 j1 i/o72 j0 t u i/o178 gx2 i/o180 gx4 i/o183 gx7 vcc vcc i/o80 k0 i/o77 j5 i/o75 j3 u v i/o182 gx6 n/c i/o169 fx1 i/o172 fx4 i/o86 k6 i/o83 k3 i/o81 k1 i/o79 j7 v w i/o168 fx0 i/o170 fx2 i/o173 fx5 gnd i/o143 bx7 vcc i/o150 cx6 i/o145 cx1 vcc i/o153 dx1 i/o123 p3 vcc i/o96 m0 vcc i/o104 n0 i/o111 n7 vcc i/o119 o7 gnd i/o87 k7 i/o84 k4 i/o82 k2 w y i/o171 fx3 i/o174 fx6 gnd i/o141 bx5 i/o138 bx2 i/o136 bx0 i/o147 cx3 i/o158 dx6 i/o156 dx4 clk2 i/o132 ax4 i/o121 p1 i/o125 p5 i/o99 m3 i/o101 m5 i/o106 n2 i/o110 n6 i/o115 o3 i/o118 o6 gnd tms i/o85 k5 y aa i/o175 fx7 gnd i/o142 bx6 i/o140 bx4 i/o151 cx7 i/o149 cx5 i/o144 cx0 i/o157 dx5 i/o154 dx2 i/o134 ax6 i/o130 ax2 i/o128 ax0 clk1 i/o127 p7 i/o100 m4 i/o103 m7 i/o108 n4 i/o109 n5 i/o113 o1 i/o116 o4 gnd tck aa ab gnd n/c i/o139 bx3 i/o137 bx1 i/o148 cx4 i/o146 cx2 i/o159 dx7 i/o155 dx3 i/o135 ax7 i/o133 ax5 i/o129 ax1 i/o120 p0 i/o124 p4 i/o126 p6 i/o97 m1 i/o102 m6 i/o105 n1 i/o107 n3 i/o112 o0 i/o114 o2 i/o117 o5 gnd ab 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pin designations clk gnd i i/o n/c vcc tdi tck tms tdo = = = = = = = = = = i/o cell pal block clock ground input input/output no connect supply voltage test data in test clock test mode select test data out c7 m4a3.512.256_388bga
60 ispmach 4a family ispmach 4a product ordering information ispmach 4a devices commercial and industrial - 3.3v and 5v lattice programmable logic products are available with several ordering options. the order number (valid combination) is formed by a combina- tion of: 1. use 5.5ns for new designs. 128 family type m4a3- = ispmach 4a family low voltage advanced feature (3.3-v v cc ) m4a5- = ispmach 4a family advanced feature (5-v v cc ) m4a3- 256 y c macrocell density 32 = 32 macrocells 192 = 192 macrocells 64 = 64 macrocells 256 = 256 macrocells 96 = 96 macrocells 384 = 384 macrocells 128 = 128 macrocells 512 = 512 macrocells i/os /32 = 32 i/os in 44-pin plcc, 44-pin tqfp or 48-pin tqfp /48 = 48 i/os in 100-pin tqfp /64 = 64 i/os in 100-pin tqfp, 100-pin pqfp, or 100-ball cabga /96 = 96 i/os in 144-pin tqfp or 144-ball fpbga /128 = 128 i/os in 208-pin pqfp, 256-ball bga or 256-ball fpbga /160 = 160 i/os in 208-pin pqfp /192 = 192 i/os in 256-ball bga or 256-ball fpbga /256 = 256 i/os in 388-ball fpbga operating conditions c = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package type sa = ball grid array (bga) j = plastic leaded chip carrier (plcc) jn = lead-free plastic leaded chip carrier (plcc) v = thin quad flat pack (tqfp) vn = lead-free thin quad flat pack (tqfp) y = plastic quad flat pack (pqfp) yn = lead-fee plastic quad flat pack (pqfp) fa = fine-pitch ball grid array (fpbga) fan = lead-free fine-pitch ball grid array (fpbga) ca = chip-array ball grid array (cabga) speed -5 = 5.0 ns t pd -55 = 5.5 ns t pd -6 = 6.0 ns t pd -65 = 6.5 ns t pd -7 = 7.5 ns t pd -10 = 10 ns t pd -12 = 12 ns t pd -14 = 14 ns t pd -7 48 = 48-pin tqfp for m4a3-32/32 or m4a3-64/32 m4a5-32/32 or m4a5-64/32 / *package obsolete, contact factory. conventional packaging 3.3v commercial combinations m4a3-32/32 -5, -7, -10 jc, vc, vc48 m4a3-64/32 -55, -7, -10 jc, vc, vc48 m4a3-64/64 vc m4a3-96/48 vc m4a3-128/64 yc, vc, cac m4a3-192/96 -6, -7, -10 vc, fac m4a3-256/128 -55, -65 1 , -7, -10 yc, fac, sac m4a3-256/160 -7, -10 yc m4a3-256/192 fac m4a3-384/160 -65, -10, -12 yc m4a3-384/192 sac, fac m4a3-512/160 -7, -10, -12 yc m4a3-512/192 fac m4a3-512/256 fac 3.3v industrial combinations m4a3-32/32 -7, -10, -12 ji, vi, vi48 m4a3-64/32 ji, vi, vi48 m4a3-64/64 vi m4a3-96/48 vi m4a3-128/64 yi, vi, cai m4a3-192/96 vi, fai m4a3-256/128 yi, fai, sai m4a3-256/160 -10, -12 yi m4a3-256/192 fai m4a3-384/160 -10, -12, -14 yi m4a3-384/192 fai m4a3-512/160 yi m4a3-512/192 fai m4a3-512/256 fai
ispmach 4a family 61 most ispmach devices are dual-marked with both commercial and industrial grades. the industrial speed grade is slower, i.e., m4a3-256/128-7yc-10yi valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local lattice sales offic e to confirm availability of specific valid combinations and to check on newly released combinations. 5v industrial combinations m4a5-32/32 -7, -10, -12 ji, vi, vi48 m4a5-64/32 -7, -10, -12 ji, vi, vi48 m4a5-96/48 vi m4a5-128/64 yi, vi m4a5-192/96 -7, -10, -12 vi m4a5-256/128 -10, -12 yi 5v commercial combinations m4a5-32/32 -5, -7, -10, jc, vc, vc48 m4a5-64/32 -55, -7, -10 jc, vc, vc48 m4a5-96/48 vc m4a5-128/64 yc, vc m4a5-192/96 -6, -7, -10 vc m4a5-256/128 -65, -7, -10 yc lead-free packaging 3.3v commercial combinations m4a3-32/32 -5, -7, -10 vnc, vnc48, jnc m4a3-64/32 -55, -7, -10 vnc, vnc48, jnc m4a3-64/64 vnc m4a3-128/64 vnc m4a3-192/96 -6, -7, -10 vnc m4a3-256/128 -55, -7, -10 fanc, ync m4a3-256/160 -7, -10 ync m4a3-256/192 fanc m4a3-384/192 -65, -10, -12 fanc m4a3-512/192 -7, -10, -12 fanc 3.3v industrial combinations m4a3-32/32 -7, -10, -12 vni, vni48, jni m4a3-64/32 vni, vni48, jni m4a3-64/64 vni m4a3-128/64 vni m4a3-192/96 -10, -12 vni m4a3-256/128 fani, yni m4a3-256/160 yni m4a3-256/192 -10, -12, -14 fani m4a3-384/192 fani m4a3-512/192 fani 5v industrial combinations m4a5-32/32 -7, -10, -12 vni, vni48, jni m4a5-64/32 vni, vni48, jni m4a5-96/48 vni m4a5-128/64 vni, yni m4a5-192/96 vni m4a5-256/128 yni 5v commercial combinations m4a5-32/32 -5, -7, -10 vnc, vnc48, jnc m4a5-64/32 -55, -7, -10 vnc, vnc48, jnc m4a5-96/48 vnc m4a5-128/64 vnc, ync m4a5-192/96 -6, -7, -10 vnc m4a5-256/128 -65, -7, -10 ync
62 ispmach 4a family revision history ? 2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. date version change summary - k previous lattice release. august 2006 l updated for lead-free package options. september 2006 m revised m4a3-256/160 208-pin pqfp connection diagram.

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